fifoasi.fit.rpt

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

Fitter report for fifoasi
Fri Sep 24 18:09:23 2004
Version 4.1 Build 181 06/29/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Floorplan View
  7. Pin-Out File
  8. Fitter Resource Usage Summary
  9. Input Pins
 10. Output Pins
 11. Bidir Pins
 12. I/O Bank Usage
 13. All Package Pins
 14. PLL Summary
 15. PLL Usage
 16. Output Pin Load For Reported TCO
 17. Fitter Resource Utilization by Entity
 18. Delay Chain Summary
 19. Pad To Core Delay Chain Fanout
 20. Control Signals
 21. Global & Other Fast Signals
 22. Non-Global High Fan-Out Signals
 23. Fitter RAM Summary
 24. Interconnect Usage Summary
 25. LAB Logic Elements
 26. LAB-wide Signals
 27. LAB Signals Sourced
 28. LAB Signals Sourced Out
 29. LAB Distinct Inputs
 30. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Fri Sep 24 18:09:23 2004    ;
; Quartus II Version    ; 4.1 Build 181 06/29/2004 SJ Full Version ;
; Revision Name         ; fifoasi                                  ;
; Top-level Entity Name ; fifo_asi                                 ;
; Family                ; Cyclone                                  ;
; Device                ; EP1C4F324C8                              ;
; Timing Models         ; Production                               ;
; Total logic elements  ; 1,929 / 4,000 ( 48 % )                   ;
; Total pins            ; 157 / 249 ( 63 % )                       ;
; Total memory bits     ; 32,768 / 78,336 ( 41 % )                 ;
; Total PLLs            ; 2 / 2 ( 100 % )                          ;
+-----------------------+------------------------------------------+