fifoasi.tcl

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.

# Quartus II: Generate Tcl File for Project
# File: fifoasi.tcl
# Generated on: Fri Sep 10 09:51:13 2004

# Load Quartus II Tcl Project package
package require ::quartus::project

set need_to_close_project 0
set make_assignments 1

# Check that the right project is open
if {[is_project_open]} {
	if {[string compare $quartus(project) "fifoasi"]} {
		puts "Project fifoasi is not open"
		set make_assignments 0
	}
} else {
	# Only open if not already open
	if {[project_exists fifoasi]} {
		project_open -revision fifoasi fifoasi
	} else {
		project_new -revision fifoasi fifoasi
	}
	set need_to_close_project 1
}

# Make assignments
if {$make_assignments} {
	set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
	set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:13:03  AUGUST 30, 2004"
	set_global_assignment -name LAST_QUARTUS_VERSION 4.1
	set_global_assignment -name VERILOG_FILE uncode.v
	set_global_assignment -name VERILOG_FILE asitodsp.v
	set_global_assignment -name VERILOG_FILE dsptoasi.v
	set_global_assignment -name BDF_FILE fifo_asi.bdf
	set_global_assignment -name BDF_FILE 32to8ddf.bdf
	set_global_assignment -name BDF_FILE 8to32ddf.bdf
	set_global_assignment -name VECTOR_WAVEFORM_FILE ../VWFA/VWFA.vwf
	set_global_assignment -name MIN_TCO_REQUIREMENT 5ns
	set_global_assignment -name TPD_REQUIREMENT 15ns
	set_global_assignment -name TSU_REQUIREMENT 15ns
	set_global_assignment -name TCO_REQUIREMENT 15ns
	set_global_assignment -name TH_REQUIREMENT 5ns
	set_global_assignment -name FMAX_REQUIREMENT "27.0 MHz" -section_id ASICLK
	set_global_assignment -name DUTY_CYCLE 50 -section_id ASICLK
	set_global_assignment -name INVERT_BASE_CLOCK OFF -section_id ASICLK
	set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ASICLK
	set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ASICLK
	set_global_assignment -name FMAX_REQUIREMENT "100.0 MHz" -section_id DSPCLK
	set_global_assignment -name DUTY_CYCLE 50 -section_id DSPCLK
	set_global_assignment -name INVERT_BASE_CLOCK OFF -section_id DSPCLK
	set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id DSPCLK
	set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id DSPCLK
	set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
	set_global_assignment -name FAMILY Cyclone
	set_global_assignment -name TOP_LEVEL_ENTITY fifo_asi
	set_global_assignment -name DEVICE EP1C4F324C8
	set_global_assignment -name MINIMUM_TPD_REQUIREMENT 5ns
	set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off
	set_instance_assignment -name CLOCK_SETTINGS ASICLK -to ASICLK
	set_instance_assignment -name CLOCK_SETTINGS DSPCLK -to DSPCLK

	# Commit assignments
	export_assignments

	# Close project
	if {$need_to_close_project} {
		project_close
	}
}