fifoasi.fit.summary

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

Flow Status : Successful - Fri Sep 24 18:09:23 2004
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : fifoasi
Top-level Entity Name : fifo_asi
Family : Cyclone
Device : EP1C4F324C8
Timing Models : Production
Total logic elements : 1,929 / 4,000 ( 48 % )
Total pins : 157 / 249 ( 63 % )
Total memory bits : 32,768 / 78,336 ( 41 % )
Total PLLs : 2 / 2 ( 100 % )