uncode.v

主要完成数字电视前端信号处理和缓冲作用的verilog源代码

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.


// Generated by Quartus II Version 4.1 (Build Build 181 06/29/2004)
// CrEAted on Thu Sep 02 17:23:44 2004

//  Module Declaration
module uncode
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	OUTA, OUTB, OUTC, OUTD, SOE3, BE0, CE, EA, LFI, Q1, Q2, Q3, Q4, Q5, 
	Q6, Q7, Q0, Q8, INA, INB, INC, IND, INE, Q9, DSPIO
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input [15:0] OUTA;
	input [15:0] OUTB;
	input [15:0] OUTC;
	input [15:0] OUTD;
	input SOE3;
	input BE0;
	input [3:0] CE;
	input [9:0] EA;
	input [3:0] LFI;
	output Q1;
	output Q2;
	output Q3;
	output Q4;
	output Q5;
	output Q6;
	output Q7;
	output Q0;
	output Q8;
	output [15:0] INA;
	output [15:0] INB;
	output [15:0] INC;
	output [15:0] IND;
	output [15:0] INE;
	output Q9;
	inout [15:0] DSPIO;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
		

	parameter address0 = 10'b00_0000_0000;
	parameter address1 = 10'b00_0000_0001;
	parameter address2 = 10'b00_0000_0010;
	parameter address3 = 10'b00_0000_0011;
	parameter address8 = 10'b00_0000_0100;
	
	parameter address4 = 10'b000000_1000;
	parameter address5 = 10'b00_0000_1001;
	parameter address6 = 10'b00_0000_1010;
	parameter address7 = 10'b00_0000_1011;
	parameter address9 = 10'b00_0000_1100;
	
	assign Q0=(EA==address0)? 1'b1:1'b0;
	assign Q1=(EA==address1)? 1'b1:1'b0;
	assign Q2=(EA==address2)? 1'b1:1'b0;
	assign Q3=(EA==address3)? 1'b1:1'b0;
	assign Q4=(EA==address4)? 1'b1:1'b0;
	assign Q5=(EA==address5)? 1'b1:1'b0;
	assign Q6=(EA==address6)? 1'b1:1'b0;
	assign Q7=(EA==address7)? 1'b1:1'b0;
	assign Q8=(EA==address8)? 1'b1:1'b0;
	assign Q9=(EA==address9)? 1'b1:1'b0;
	
    reg [15:0] DSPIO;
    reg [15:0] INA;
	reg [15:0] INB;
	reg [15:0] INC;
	reg [15:0] IND;
	reg [15:0] INE;
	

	
always@(EA or CE or OUTA or OUTB or OUTC or OUTD or DSPIO )
	if({SOE3,CE}==5'b00111)
	begin 
	case(EA)
	address0:
	begin
	INA=DSPIO;INB=16'bz;INC=16'bz;IND=16'bz;INE=16'bz;
	end
	address1:begin
	INA=16'bz;INB=DSPIO;INC=16'bz;IND=16'bz;INE=16'bz;
	end
	address2:
	begin
	INA=16'bz;INB=16'bz;INC=DSPIO;IND=16'bz;INE=16'bz;
	end
	address3:
	begin
	INA=16'bz;INB=16'bz;INC=16'bz;IND=DSPIO;INE=16'bz;
	end
	address8:
	begin
	INA=16'bz;INB=16'bz;INC=16'bz;IND=16'bz;INE=DSPIO;
	end
	address4:DSPIO=OUTA;
	address5:DSPIO=OUTB;
	address6:DSPIO=OUTC;
	address7:DSPIO=OUTD;
	address9:DSPIO={12'h0000,LFI};
	default:
	begin
	INA=16'bz;INB=16'bz;INC=16'bz;IND=16'bz;INE=16'bz;
	DSPIO=16'bz;
	end
		endcase
	end
	else
	begin
	INA=16'bz;INB=16'bz;INC=16'bz;IND=16'bz;INE=16'bz;
	DSPIO=16'bz;
	end
	
   endmodule