caiyang.vhd

基于FPGA设计ADC0809采样控制器原代码

--程序名:caiyang.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY caiyang IS
 PORT(D:IN STD_LOGIC_vECTOR(7 DOWNTO 0);
         CLK,EOC:IN STD_LOGIC;
  LOCK1,ALE,START,OE,ADDA:OUT STD_LOGIC;
   Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
 END caiyang;
 ARCHITECTURE behav OF caiyang IS
TYPE states IS(st0,st1,st2,st3,st4,st5,st6);
SIGNAL current_state, next_state:states:=st0;
SIGNAL REGL:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK:STD_LOGIC;
BEGIN
ADDA<='1';LOCK1<=LOCK;
PRO:PROCESS(current_state,EOC)BEGIN
CASE current_state IS
WHEN st0=>ALE<='0';START<='0';OE<='0';LOCK<='0';next_state<=st1;
WHEN st1=>ALE<='1';START<='0';OE<='0';LOCK<='0';next_state<=st2;
WHEN st2=>ALE<='0';START<='1';OE<='0';LOCK<='0';next_state<=st3;
WHEN st3=>ALE<='0';START<='0';OE<='0';LOCK<='0';
 IF(EOC='1')THEN next_state<=st3;
ELSE next_state<=st4;
END IF;
WHEN st4=>ALE<='0';START<='0';OE<='0';LOCK<='0';
IF(EOC='0')THEN next_state<=st4;
ELSE next_state<=st5;
END IF;
WHEN st5=>ALE<='0';START<='0';OE<='1';LOCK<='0';next_state<=st6;
WHEN st6=>ALE<='0';START<='0';OE<='1';LOCK<='1';next_state<=st0;
WHEN OTHERS=>ALE<='0';START<='0';OE<='0';LOCK<='0';next_state<=st0;
END CASE;
END PROCESS PRO;
 PROCESS(CLK)
BEGIN
  IF(CLK'EVENT AND CLK='1')THEN
    current_state<=next_state;
    END IF;
   END PROCESS;
     PROCESS(LOCK)
   BEGIN
   IF LOCK='1' AND LOCK'EVENT THEN REGL<=D;
   END IF;
END PROCESS;
    Q<=REGL;
END behav;