caiyang.fit

基于FPGA设计ADC0809采样控制器原代码

-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 03/27/2005 11:51:34      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "caiyang"
BEGIN

    DEVICE = "EPF10K10LC84-3";

    "CLK"                          : INPUT_PIN  = 1      ;
    "D0"                           : INPUT_PIN  = 42     ;
    "D1"                           : INPUT_PIN  = 44     ;
    "D2"                           : INPUT_PIN  = 84     ;
    "D3"                           : INPUT_PIN  = 43     ;
    "D4"                           : INPUT_PIN  = 29     ;
    "D5"                           : INPUT_PIN  = 28     ;
    "D6"                           : INPUT_PIN  = 24     ;
    "D7"                           : INPUT_PIN  = 27     ;
    "EOC"                          : INPUT_PIN  = 2      ;
    "ADDA"                         : OUTPUT_PIN = 70     ;
    "ALE"                          : OUTPUT_PIN = 66     ;
    "LOCK1"                        : OUTPUT_PIN = 51     ;
    "OE"                           : OUTPUT_PIN = 64     ;
    "Q0"                           : OUTPUT_PIN = 60     ;
    "Q1"                           : OUTPUT_PIN = 59     ;
    "Q2"                           : OUTPUT_PIN = 61     ;
    "Q3"                           : OUTPUT_PIN = 83     ;
    "Q4"                           : OUTPUT_PIN = 62     ;
    "Q5"                           : OUTPUT_PIN = 47     ;
    "Q6"                           : OUTPUT_PIN = 65     ;
    "Q7"                           : OUTPUT_PIN = 58     ;
    "START"                        : OUTPUT_PIN = 22     ;
    ":24"                          : LOCATION   = LC8_B18;  -- current_state2
    ":25"                          : LOCATION   = LC7_B18;  -- current_state1
    ":26"                          : LOCATION   = LC4_B18;  -- current_state0
    ":31"                          : LOCATION   = LC7_C14;  -- REGL7
    ":32"                          : LOCATION   = LC5_B18;  -- REGL6
    ":33"                          : LOCATION   = LC4_C14;  -- REGL5
    ":34"                          : LOCATION   = LC1_C14;  -- REGL4
    ":35"                          : LOCATION   = LC6_C14;  -- REGL3
    ":36"                          : LOCATION   = LC2_C14;  -- REGL2
    ":37"                          : LOCATION   = LC5_C14;  -- REGL1
    ":38"                          : LOCATION   = LC3_C14;  -- REGL0
    ":308"                         : LOCATION   = LC1_B18;
    ":318"                         : LOCATION   = LC2_B18;
    ":375"                         : LOCATION   = LC6_B18;
    ":396"                         : LOCATION   = LC3_B18;

END;

INTERNAL_INFO "caiyang"
BEGIN
	DEVICE = EPF10K10LC84-3;
    OD4P1   : LORAX = "1:FB4->LC8_B18,->LC7_B18,->LC4_B18|";
    OD3P42  : LORAX = "1:FB3|2:FH3R2,PA5R2C13->LC3_C14||";
    OD2P44  : LORAX = "1:FB2|2:FH2R2,PA6R2C13->LC5_C14||";
    OD0P84  : LORAX = "1:FB0|2:FH0R2,PA0R2C13->LC2_C14||";
    OD5P43  : LORAX = "1:FB5|2:CH1R2,PA7R2C13->LC6_C14||";
    OH12R2P29 : LORAX = "1:G40R2,PA19R2C13->LC1_C14|";
    OH10R2P28 : LORAX = "1:G41R2,PA18R2C13->LC4_C14|";
    OH13R1P24 : LORAX = "1:G14R1,PA20R1C17->LC5_B18|";
    OH8R2P27 : LORAX = "1:G13R2,PA4R2C13->LC7_C14|";
    OD1P2   : LORAX = "1:FB1|2:FH1R1,PA13R1C17->LC8_B18,->LC7_B18,->LC4_B18||";
    LC7_C14 : LORAX = "1:MSW6R2C13,G53R2->OH6R2P58|";
    LC5_B18 : LORAX = "1:MSW4R1C17,HHR30R1->OH4R1P65|";
    LC4_C14 : LORAX = "1:MSW3R2C13,V10C13->OV2C13P47|";
    LC1_C14 : LORAX = "1:MSW0R2C13,HHR23R2->OH0R2P62|";
    LC6_C14 : LORAX = "1:MSW6R2C12,V19C12->OV1C12P83|";
    LC2_C14 : LORAX = "1:MSW2R2C12,G17R2->OH2R2P61|";
    LC5_C14 : LORAX = "1:MSW4R2C13,HHR36R2->OH4R2P59|";
    LC3_C14 : LORAX = "1:MSW3R2C12,HHR9R2->OH3R2P60|";
    LC1_B18 : LORAX = "1:MSW1R1C16,G22R1->OH9R1P22|";
    LC2_B18 : LORAX = "1:MSW2R1C16,HHR0R1->OH2R1P66|";
    LC6_B18 : LORAX = "1:MSW6R1C16,HHR31R1->OH6R1P64|";
    LC3_B18 : LORAX = "1:MSW2R1C17,V6C17->OV2C17P51,2:HHR15R2,PA8R2C13->LC7_C14,->LC4_C14,->LC1_C14,->LC6_C14,->LC2_C14,->LC5_C14,->LC3_C14||";
	LC8_B18 : LORAX2 = "OD1P2, LC4_B18, LC7_B18, LC8_B18";
	LC7_B18 : LORAX2 = "OD1P2, LC4_B18, LC7_B18, LC8_B18";
	LC4_B18 : LORAX2 = "OD1P2, LC4_B18, LC7_B18, LC8_B18";
	LC7_C14 : LORAX2 = "OH8R2P27, X, X, X";
	LC5_B18 : LORAX2 = "OH13R1P24, X, X, X";
	LC4_C14 : LORAX2 = "OH10R2P28, X, X, X";
	LC1_C14 : LORAX2 = "OH12R2P29, X, X, X";
	LC6_C14 : LORAX2 = "OD5P43, X, X, X";
	LC2_C14 : LORAX2 = "OD0P84, X, X, X";
	LC5_C14 : LORAX2 = "OD2P44, X, X, X";
	LC3_C14 : LORAX2 = "OD3P42, X, X, X";
	LC1_B18 : LORAX2 = "X, LC4_B18, LC7_B18, LC8_B18";
	LC2_B18 : LORAX2 = "X, LC4_B18, LC7_B18, LC8_B18";
	LC6_B18 : LORAX2 = "X, LC4_B18, LC7_B18, LC8_B18";
	LC3_B18 : LORAX2 = "X, X, LC7_B18, LC8_B18";
END;