📄 caiyang.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 2/ 96( 2%) 0/ 48( 0%) 3/ 48( 6%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
C: 5/ 96( 5%) 0/ 48( 0%) 4/ 48( 8%) 3/16( 18%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\maxplus2\muxfile\caiyang.rpt
caiyang
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 9 :396
INPUT 3 CLK
Device-Specific Information: c:\maxplus2\muxfile\caiyang.rpt
caiyang
** EQUATIONS **
CLK : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
EOC : INPUT;
-- Node name is 'ADDA'
-- Equation name is 'ADDA', type is output
ADDA = VCC;
-- Node name is 'ALE'
-- Equation name is 'ALE', type is output
ALE = _LC2_B18;
-- Node name is ':26' = 'current_state0'
-- Equation name is 'current_state0', location is LC4_B18, type is buried.
current_state0 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = !current_state0 & !current_state2
# current_state1 & !current_state2 & EOC
# !current_state0 & !current_state1 & EOC;
-- Node name is ':25' = 'current_state1'
-- Equation name is 'current_state1', location is LC7_B18, type is buried.
current_state1 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = current_state0 & !current_state1
# current_state0 & !current_state2 & EOC
# !current_state0 & current_state1 & !current_state2;
-- Node name is ':24' = 'current_state2'
-- Equation name is 'current_state2', location is LC8_B18, type is buried.
current_state2 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = current_state0 & current_state1 & !current_state2 & !EOC
# !current_state1 & current_state2;
-- Node name is 'LOCK1'
-- Equation name is 'LOCK1', type is output
LOCK1 = _LC3_B18;
-- Node name is 'OE'
-- Equation name is 'OE', type is output
OE = _LC6_B18;
-- Node name is 'Q0'
-- Equation name is 'Q0', type is output
Q0 = REGL0;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = REGL1;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = REGL2;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = REGL3;
-- Node name is 'Q4'
-- Equation name is 'Q4', type is output
Q4 = REGL4;
-- Node name is 'Q5'
-- Equation name is 'Q5', type is output
Q5 = REGL5;
-- Node name is 'Q6'
-- Equation name is 'Q6', type is output
Q6 = REGL6;
-- Node name is 'Q7'
-- Equation name is 'Q7', type is output
Q7 = REGL7;
-- Node name is ':38' = 'REGL0'
-- Equation name is 'REGL0', location is LC3_C14, type is buried.
REGL0 = DFFE( D0, _LC3_B18, VCC, VCC, VCC);
-- Node name is ':37' = 'REGL1'
-- Equation name is 'REGL1', location is LC5_C14, type is buried.
REGL1 = DFFE( D1, _LC3_B18, VCC, VCC, VCC);
-- Node name is ':36' = 'REGL2'
-- Equation name is 'REGL2', location is LC2_C14, type is buried.
REGL2 = DFFE( D2, _LC3_B18, VCC, VCC, VCC);
-- Node name is ':35' = 'REGL3'
-- Equation name is 'REGL3', location is LC6_C14, type is buried.
REGL3 = DFFE( D3, _LC3_B18, VCC, VCC, VCC);
-- Node name is ':34' = 'REGL4'
-- Equation name is 'REGL4', location is LC1_C14, type is buried.
REGL4 = DFFE( D4, _LC3_B18, VCC, VCC, VCC);
-- Node name is ':33' = 'REGL5'
-- Equation name is 'REGL5', location is LC4_C14, type is buried.
REGL5 = DFFE( D5, _LC3_B18, VCC, VCC, VCC);
-- Node name is ':32' = 'REGL6'
-- Equation name is 'REGL6', location is LC5_B18, type is buried.
REGL6 = DFFE( D6, _LC3_B18, VCC, VCC, VCC);
-- Node name is ':31' = 'REGL7'
-- Equation name is 'REGL7', location is LC7_C14, type is buried.
REGL7 = DFFE( D7, _LC3_B18, VCC, VCC, VCC);
-- Node name is 'START'
-- Equation name is 'START', type is output
START = _LC1_B18;
-- Node name is ':308'
-- Equation name is '_LC1_B18', type is buried
_LC1_B18 = LCELL( _EQ004);
_EQ004 = !current_state0 & current_state1 & !current_state2;
-- Node name is ':318'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = LCELL( _EQ005);
_EQ005 = current_state0 & !current_state1 & !current_state2;
-- Node name is ':375'
-- Equation name is '_LC6_B18', type is buried
_LC6_B18 = LCELL( _EQ006);
_EQ006 = current_state0 & current_state2
# current_state1 & current_state2;
-- Node name is ':396'
-- Equation name is '_LC3_B18', type is buried
_LC3_B18 = LCELL( _EQ007);
_EQ007 = current_state1 & current_state2;
Project Information c:\maxplus2\muxfile\caiyang.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 11,256K
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