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Minimum period: 6.067ns (Maximum Frequency: 164.826MHz) Minimum input arrival time before clock: 5.343ns Maximum output required time after clock: 8.543ns Maximum combinational path delay: 8.063ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "pn_code.v"Module <pn_encode> compiledNo errors in compilationAnalysis of file <pn_encode.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <pn_encode>.Module <pn_encode> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <pn_encode>. Related source file is pn_code.v. Found 1-bit register for signal <flag_tra>. Found 1-bit xor2 for signal <$n0001> created at line 28. Found 4-bit comparator lessequal for signal <$n0005> created at line 37. Found 1-bit xor2 for signal <$n0007>. Found 4-bit up counter for signal <flag_tra_counter>. Found 4-bit register for signal <x>. Summary: inferred 1 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Comparator(s).Unit <pn_encode> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 5 1-bit register : 5# Counters : 1 4-bit up counter : 1# Comparators : 1 4-bit comparator lessequal : 1# Xors : 2 1-bit xor2 : 2==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <pn_encode> ...Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block pn_encode, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 Number of Slices: 7 out of 768 0% Number of Slice Flip Flops: 9 out of 1536 0% Number of 4 input LUTs: 12 out of 1536 0% Number of bonded IOBs: 5 out of 96 5% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk_pn | BUFGP | 9 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 6.471ns (Maximum Frequency: 154.536MHz) Minimum input arrival time before clock: 5.344ns Maximum output required time after clock: 8.543ns Maximum combinational path delay: 8.063ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "pn_code.v"Module <pn_encode> compiledNo errors in compilationAnalysis of file <pn_encode.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <pn_encode>.Module <pn_encode> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <pn_encode>. Related source file is pn_code.v. Found 1-bit register for signal <flag_tra>. Found 1-bit xor2 for signal <$n0001> created at line 28. Found 4-bit comparator lessequal for signal <$n0005> created at line 37. Found 1-bit xor2 for signal <$n0007>. Found 4-bit up counter for signal <flag_tra_counter>. Found 4-bit register for signal <x>. Summary: inferred 1 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Comparator(s).Unit <pn_encode> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 5 1-bit register : 5# Counters : 1 4-bit up counter : 1# Comparators : 1 4-bit comparator lessequal : 1# Xors : 2 1-bit xor2 : 2==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <pn_encode> ...Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block pn_encode, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 Number of Slices: 8 out of 768 1% Number of Slice Flip Flops: 9 out of 1536 0% Number of 4 input LUTs: 13 out of 1536 0% Number of bonded IOBs: 5 out of 96 5% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk_pn | BUFGP | 9 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 5.897ns (Maximum Frequency: 169.578MHz) Minimum input arrival time before clock: 5.344ns Maximum output required time after clock: 8.543ns Maximum combinational path delay: 8.063ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "pn_code.v"Module <pn_encode> compiledNo errors in compilationAnalysis of file <pn_encode.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <pn_encode>.Module <pn_encode> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <pn_encode>. Related source file is pn_code.v. Found 1-bit register for signal <flag_tra>. Found 1-bit xor2 for signal <$n0001> created at line 28. Found 4-bit comparator lessequal for signal <$n0005> created at line 37. Found 1-bit xor2 for signal <$n0007>. Found 4-bit up counter for signal <flag_tra_counter>. Found 4-bit register for signal <x>. Summary: inferred 1 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Comparator(s).Unit <pn_encode> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 5 1-bit register : 5# Counters : 1 4-bit up counter : 1# Comparators : 1 4-bit comparator lessequal : 1# Xors : 2 1-bit xor2 : 2==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <pn_encode> ...Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block pn_encode, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 Number of Slices: 8 out of 768 1% Number of Slice Flip Flops: 9 out of 1536 0% Number of 4 input LUTs: 13 out of 1536 0% Number of bonded IOBs: 5 out of 96 5% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk_pn | BUFGP | 9 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 5.897ns (Maximum Frequency: 169.578MHz) Minimum input arrival time before clock: 5.344ns Maximum output required time after clock: 8.543ns Maximum combinational path delay: 8.063ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
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