__projnav.log

系数为4的扰码生成器

---------------
Speed Grade: -6

   Minimum period: 5.166ns (Maximum Frequency: 193.573MHz)
   Minimum input arrival time before clock: 4.983ns
   Maximum output required time after clock: 8.543ns
   Maximum combinational path delay: 8.063ns

=========================================================================
Completed process "Synthesize".



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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "pn_code.v"
Module <pn_encode> compiled
No errors in compilation
Analysis of file <pn_encode.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <pn_encode>.
Module <pn_encode> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <pn_encode>.
    Related source file is pn_code.v.
    Found 1-bit register for signal <flag_tra>.
    Found 1-bit xor2 for signal <$n0001> created at line 28.
    Found 5-bit comparator lessequal for signal <$n0006> created at line 36.
    Found 1-bit xor2 for signal <$n0008>.
    Found 5-bit up counter for signal <flag_tra_counter>.
    Found 4-bit register for signal <x>.
    Summary:
	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <pn_encode> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 5
  1-bit register                   : 5
# Counters                         : 1
  5-bit up counter                 : 1
# Comparators                      : 1
  5-bit comparator lessequal       : 1
# Xors                             : 2
  1-bit xor2                       : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <pn_encode> ...
Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block pn_encode, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       9  out of    768     1%  
 Number of Slice Flip Flops:            10  out of   1536     0%  
 Number of 4 input LUTs:                14  out of   1536     0%  
 Number of bonded IOBs:                  5  out of     96     5%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_pn                             | BUFGP                  | 10    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.067ns (Maximum Frequency: 164.826MHz)
   Minimum input arrival time before clock: 5.343ns
   Maximum output required time after clock: 8.543ns
   Maximum combinational path delay: 8.063ns

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "pn_code.v"
Module <pn_encode> compiled
No errors in compilation
Analysis of file <pn_encode.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <pn_encode>.
Module <pn_encode> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <pn_encode>.
    Related source file is pn_code.v.
    Found 1-bit register for signal <flag_tra>.
    Found 1-bit xor2 for signal <$n0001> created at line 28.
    Found 5-bit comparator lessequal for signal <$n0006> created at line 36.
    Found 1-bit xor2 for signal <$n0008>.
    Found 5-bit up counter for signal <flag_tra_counter>.
    Found 4-bit register for signal <x>.
    Summary:
	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <pn_encode> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 5
  1-bit register                   : 5
# Counters                         : 1
  5-bit up counter                 : 1
# Comparators                      : 1
  5-bit comparator lessequal       : 1
# Xors                             : 2
  1-bit xor2                       : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <pn_encode> ...
Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block pn_encode, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       9  out of    768     1%  
 Number of Slice Flip Flops:            10  out of   1536     0%  
 Number of 4 input LUTs:                15  out of   1536     0%  
 Number of bonded IOBs:                  5  out of     96     5%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_pn                             | BUFGP                  | 10    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 6.067ns (Maximum Frequency: 164.826MHz)
   Minimum input arrival time before clock: 5.343ns
   Maximum output required time after clock: 8.543ns
   Maximum combinational path delay: 8.063ns

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "pn_code.v"
Module <pn_encode> compiled
No errors in compilation
Analysis of file <pn_encode.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <pn_encode>.
Module <pn_encode> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <pn_encode>.
    Related source file is pn_code.v.
    Found 1-bit register for signal <flag_tra>.
    Found 1-bit xor2 for signal <$n0001> created at line 28.
    Found 5-bit comparator lessequal for signal <$n0007> created at line 37.
    Found 1-bit xor2 for signal <$n0010>.
    Found 5-bit up counter for signal <flag_tra_counter>.
    Found 4-bit register for signal <x>.
    Summary:
	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <pn_encode> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 5
  1-bit register                   : 5
# Counters                         : 1
  5-bit up counter                 : 1
# Comparators                      : 1
  5-bit comparator lessequal       : 1
# Xors                             : 2
  1-bit xor2                       : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <pn_encode> ...
Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block pn_encode, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       9  out of    768     1%  
 Number of Slice Flip Flops:            10  out of   1536     0%  
 Number of 4 input LUTs:                15  out of   1536     0%  
 Number of bonded IOBs:                  5  out of     96     5%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_pn                             | BUFGP                  | 10    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6