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Project Navigator Auto-Make Log File-------------------------------------
Compiling source file "pn_code.v"tdtfi(verilog) completed successfully.
Project Navigator Auto-Make Log File-------------------------------------
Compiling source file "pn_code.v"tdtfi(verilog) completed successfully.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "pn_code.v"Module <pn_encode> compiledNo errors in compilationAnalysis of file <pn_encode.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <pn_encode>.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[3]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[2]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[1]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[0]> does not match a known FF or Latch template. Found 4 error(s). Aborting synthesis.--> Total memory usage is 47260 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "pn_code.v"Module <pn_encode> compiledNo errors in compilationAnalysis of file <pn_encode.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <pn_encode>.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[3]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[2]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[1]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[0]> does not match a known FF or Latch template. Found 4 error(s). Aborting synthesis.--> Total memory usage is 47260 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "pn_code.v"Module <pn_encode> compiledNo errors in compilationAnalysis of file <pn_encode.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <pn_encode>.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[3]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[2]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[1]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[0]> does not match a known FF or Latch template. Found 4 error(s). Aborting synthesis.--> Total memory usage is 47260 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "pn_code.v"Module <pn_encode> compiledNo errors in compilationAnalysis of file <pn_encode.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <pn_encode>.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[3]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[2]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[1]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[0]> does not match a known FF or Latch template. Found 4 error(s). Aborting synthesis.--> Total memory usage is 47260 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "pn_code.v"Module <pn_encode> compiledNo errors in compilationAnalysis of file <pn_encode.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <pn_encode>.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[3]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[2]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[1]> does not match a known FF or Latch template.ERROR:Xst:899 - pn_code.v line 15: The logic for <x[0]> does not match a known FF or Latch template. Found 4 error(s). Aborting synthesis.--> Total memory usage is 47260 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "pn_code.v"Module <pn_encode> compiledNo errors in compilationAnalysis of file <pn_encode.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <pn_encode>.Module <pn_encode> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <pn_encode>. Related source file is pn_code.v.WARNING:Xst:1306 - Output <pn_out> is never assigned.WARNING:Xst:647 - Input <data_source> is never used. Found 1-bit xor2 for signal <$n0001> created at line 22. Found 4-bit register for signal <x>. Summary: inferred 4 D-type flip-flop(s).Unit <pn_encode> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 4 1-bit register : 4# Xors : 1 1-bit xor2 : 1==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <pn_encode> ...Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block pn_encode, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -6 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "pn_code.v"Module <pn_encode> compiledNo errors in compilationAnalysis of file <pn_encode.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <pn_encode>.Module <pn_encode> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <pn_encode>. Related source file is pn_code.v. Found 1-bit xor2 for signal <$n0002> created at line 22. Found 4-bit register for signal <x>. Summary: inferred 4 D-type flip-flop(s).Unit <pn_encode> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 4 1-bit register : 4# Xors : 1 1-bit xor2 : 1==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <pn_encode> ...Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block pn_encode, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-6 ⌨️ 快捷键说明
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