pn_encode.syr

系数为4的扰码生成器

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
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--> Reading design: pn_encode.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : pn_encode.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : pn_encode
Output Format                      : NGC
Target Device                      : xc2s50-6-tq144

---- Source Options
Top Module Name                    : pn_encode
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : pn_encode.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "pn_code.v"
Module <pn_encode> compiled
No errors in compilation
Analysis of file <pn_encode.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <pn_encode>.
Module <pn_encode> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <pn_encode>.
    Related source file is pn_code.v.
    Found 1-bit xor3 for signal <pn_out>.
    Found 1-bit register for signal <flag_tra>.
    Found 4-bit comparator lessequal for signal <$n0004> created at line 37.
    Found 4-bit up counter for signal <flag_tra_counter>.
    Found 4-bit register for signal <x>.
    Summary:
	inferred   1 Counter(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Xor(s).
Unit <pn_encode> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 5
  1-bit register                   : 5
# Counters                         : 1
  4-bit up counter                 : 1
# Comparators                      : 1
  4-bit comparator lessequal       : 1
# Xors                             : 1
  1-bit xor3                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <pn_encode> ...
Loading device for application Xst from file 'v50.nph' in environment E:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block pn_encode, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : pn_encode.ngr
Top Level Output File Name         : pn_encode
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 6

Macro Statistics :
# Registers                        : 6
#      1-bit register              : 5
#      4-bit register              : 1
# Adders/Subtractors               : 1
#      4-bit adder                 : 1
# Comparators                      : 1
#      4-bit comparator lessequal  : 1
# Xors                             : 1
#      1-bit xor3                  : 1

Cell Usage :
# BELS                             : 20
#      GND                         : 1
#      LUT1                        : 2
#      LUT1_L                      : 3
#      LUT2                        : 1
#      LUT3                        : 2
#      LUT3_L                      : 2
#      LUT4                        : 2
#      MUXCY                       : 3
#      VCC                         : 1
#      XORCY                       : 3
# FlipFlops/Latches                : 9
#      FDE                         : 1
#      FDR                         : 3
#      FDRE                        : 4
#      FDRS                        : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 5
#      IBUF                        : 3
#      OBUF                        : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                       8  out of    768     1%  
 Number of Slice Flip Flops:             9  out of   1536     0%  
 Number of 4 input LUTs:                12  out of   1536     0%  
 Number of bonded IOBs:                  5  out of     96     5%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_pn                             | BUFGP                  | 9     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 5.897ns (Maximum Frequency: 169.578MHz)
   Minimum input arrival time before clock: 5.344ns
   Maximum output required time after clock: 8.714ns
   Maximum combinational path delay: 8.234ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk_pn'
Delay:               5.897ns (Levels of Logic = 2)
  Source:            flag_tra_counter_2 (FF)
  Destination:       flag_tra_counter_2 (FF)
  Source Clock:      clk_pn rising
  Destination Clock: clk_pn rising

  Data Path: flag_tra_counter_2 to flag_tra_counter_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             4   1.085   1.440  flag_tra_counter_2 (flag_tra_counter_2)
     LUT3_L:I0->LO         1   0.549   0.100  _n0001_SW0 (N671)
     LUT4:I3->O            4   0.549   1.440  _n0001 (_n0001)
     FDRE:R                    0.734          flag_tra_counter_0
    ----------------------------------------
    Total                      5.897ns (2.917ns logic, 2.980ns route)
                                       (49.5% logic, 50.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_pn'
Offset:              5.344ns (Levels of Logic = 2)
  Source:            reset_pn (PAD)
  Destination:       flag_tra_counter_2 (FF)
  Destination Clock: clk_pn rising

  Data Path: reset_pn to flag_tra_counter_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             8   0.776   1.845  reset_pn_IBUF (reset_pn_IBUF)
     LUT4:I0->O            4   0.549   1.440  _n0001 (_n0001)
     FDRE:R                    0.734          flag_tra_counter_0
    ----------------------------------------
    Total                      5.344ns (2.059ns logic, 3.285ns route)
                                       (38.5% logic, 61.5% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_pn'
Offset:              8.714ns (Levels of Logic = 2)
  Source:            x_0 (FF)
  Destination:       pn_out (PAD)
  Source Clock:      clk_pn rising

  Data Path: x_0 to pn_out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRS:C->Q             2   1.085   1.206  x_0 (x_0)
     LUT3:I1->O            2   0.549   1.206  Mxor_pn_out_Xo<1>1 (pn_out_OBUF)
     OBUF:I->O                 4.668          pn_out_OBUF (pn_out)
    ----------------------------------------
    Total                      8.714ns (6.302ns logic, 2.412ns route)
                                       (72.3% logic, 27.7% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               8.234ns (Levels of Logic = 3)
  Source:            data_source (PAD)
  Destination:       pn_out (PAD)

  Data Path: data_source to pn_out
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.776   1.035  data_source_IBUF (data_source_IBUF)
     LUT3:I0->O            2   0.549   1.206  Mxor_pn_out_Xo<1>1 (pn_out_OBUF)
     OBUF:I->O                 4.668          pn_out_OBUF (pn_out)
    ----------------------------------------
    Total                      8.234ns (5.993ns logic, 2.241ns route)
                                       (72.8% logic, 27.2% route)

=========================================================================
CPU : 3.14 / 4.42 s | Elapsed : 4.00 / 5.00 s
 
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Total memory usage is 54472 kilobytes