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来自「本人初学VHDL时编的比较系统的VHDL源程序 巨实用」· 代码 · 共 32 行

library IEEE;
use IEEE.std_logic_1164.all;

entity decoder is
    port (enable:in bit;
        sel: in bit_VECTOR (2 downto 0);
        yout: out bit_VECTOR (7 downto 0)
    );
end decoder;

architecture decoder_arch of decoder is
signal z:bit_vector(7 downto 0);
begin
  with sel select
  z<="11111110"when"000",
     "11111101"when"001",
     "11111011"when"010",
     "11110111"when"011",
     "11101111"when"100",
     "11011111"when"101",
     "10111111"when"110",
     "01111111"when"111";
     process(enable)
     begin
        if enable='1'then
        yout<=z;
        else
        yout<="00000000";
        end if;
        end process;
end decoder_arch;