本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;

entity yimaqi is
    port (
        sel: in bit_VECTOR (3 downto 0);
        yout: out bit_VECTOR (6 downto 0)
    );
end yimaqi;

architecture yimaqi_arch of yimaqi is
begin
      with sel select
       yout<="1111110"when "0000",
             "0000110"when "0001",
             "1101101"when "0010",
             "1111001"when "0011",
             "0110011"when "0100",
             "1011011"when "0101",
             "1011111"when "0110",
             "1110000"when "0111",
             "1111111"when "1000",
             "1111011"when "1001",
             "1110111"when "1010",
             "1111111"when "1011",
             "1001110"when "1100",
             "1111110"when "1101",
             "1001111"when "1110",
             "1000111"when "1111";
       
       
       
end yimaqi_arch;