本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;

entity emcomp4 is
    port (
        a: in STD_LOGIC_VECTOR (3 downto 0);
        b: in STD_LOGIC_VECTOR (3 downto 0);
        equals: out STD_LOGIC
    );
end emcomp4;

architecture emcomp4_arch of emcomp4 is
begin
     comp:process(a,b)
     begin
         if a=b then
           equals<='1';
         else
           equals<='0';
         end if;
     end process comp; 
end emcomp4_arch;