and2.vhd

本人初学VHDL时编的比较系统的VHDL源程序 巨实用

library IEEE;
use IEEE.std_logic_1164.all;

entity and2 is
    port (
        c: out STD_LOGIC;
        a: in STD_LOGIC;
        b: in STD_LOGIC
    );
end and2;

architecture and2_arch of and2 is
begin
  c <= a and b ;-- <<enter your statements here>>
end and2_arch;