custom_mul.v

vhdl编写的硬件乘法器

/* 
This file is distributed without any warranty.

Stefaan Vanheesbeke 2004 ([e-mail])
You can use and distribute this free without any restriction, 
as long you don't sell this file as part of other IP cores.

In case of problems or improvements, let me know.
*/

// implementation of custom instruction for NIOSII
// Functionality : Multiplier 

// Provide following somewher in the source code or a library :
//
// #define MULSI 13
// int __mulsi3 (int a, int b)
// { 
//   return __builtin_custom_inii(MULSI, a, b); 
// }

// too bad I couldn't make it 'inlining', this should save some more lot more cycles 


// other functionality cutted out. So if you need only the multiplier,
// you can change the code for readability. 
// Hower this can be used as framework for other custom instruction opcodes


//define custominstructions opcode extensions
//copy-paste to C header file and replace ` by #
`define MULSI 13
//...

module os_accellerator_custom(clk, clk_en, reset, 
							  dataa, datab, n, 
							  result, start, done);

input clk, reset;
input clk_en; //not used

input [31:0] dataa;
input [31:0] datab;
input [7:0] n;

input start;
output done;
reg done;

output [31:0] result;
reg    [31:0] result;

reg [31:0] MA;
reg [31:0] MB;
reg [31:0] MR;

always @(posedge clk or posedge reset)
	if (reset)
		begin
			MA <= 0;
			MB <= 0;
			MR <= 0;
		end
	else
		begin
			if (start)
				case (n)

					//other custom instructions, when needed start	

					`MULSI : begin
								if (dataa < datab) //seen as signed here, 
								                   //can reduce nr of cycles by choosing smallest as loop iterator
												   //does help a lot for positive*positive and negative*positive
												   //not any help for negative*negative, because both seen as very big 
												   //unsigned values (MSB set)
									begin
										MA <= dataa;
										MB <= datab;
									end
								else
									begin
										MA <= datab;
										MB <= dataa;
									end
								MR <= 0;
							end		
				endcase

			//multiplier loop
			if (MA)
				begin
					if (MA & 1)
						MR <= MR + MB;
					MA <= MA >> 1;
					MB <= MB << 1;				
				end
		end


//multiplexer for result
always @(n)
	case (n)

		//others to add if ncry	
	
		`MULSI : result = MR; 
		
		default : result = 0;
	endcase


//multiplexer for done bit to processor
always @(n)
	case (n)

		//others to add if ncry	

		`MULSI : done = (!MA) && !start; // && !start because if result is 0 
										 // (e.g. one of the operands is zero), 
										 // I need one clock to clear the MR register

		default : done = 1;
	endcase

endmodule