memory.v.bak

用verilog编写在FLEX10K上实现的简易CPU

//general memory

module memory(clk, rst, rd_en, wt_en, addr, data_in, data_out);
	input clk, rst, rd_en, wt_en, addr, data_in;
	output data_out;
	
	wire[15:0] addr, data_in, data_out;
	
	reg[15:0]	mem[63:0];
	
	integer memindex;

	initial 
	begin
	    mem[0] = 16'b1100_0000_0011_0010;
	    mem[1] = 16'b1100_0000_0001_0100;
	    mem[2] = 16'b1000_0000_0011_0001;
	    
	    mem[3] = 16'b0011_0010_0000_0011;
	    mem[4] = 16'b0010_0010_0000_0000;
	    mem[5] = 16'b0001_0011_0001_0001;
	    mem[6] = 16'b0000_0011_0001_0010;
	end
	
	
	assign data_out = ( rd_en ) ? mem[addr] : 16'hzzzz;
	
	always@(posedge clk)
	begin
		if(rst)
			for(memindex = 7; memindex < 16; memindex = memindex + 1)
				mem[memindex] <= 16'b0000_0000_0000_0000;
		else
			if(wt_en)
				mem[addr] <= data_in;
	end
	
	endmodule