mux2.v.bak

用verilog编写在FLEX10K上实现的简易CPU

//16b two port mux 

module mux2(control, data0, data1, out, clk);
	input control, data0, data1, clk;
	output out;
	
	//reg ctrl;
	
	wire[15:0]	data0, data1, out;
	
	assign out = control ? data1 : data0;
	
	/*
	always@(posedge clk)
	if(en)
	   ctrl <= control;
	else
	   ctrl <= ctrl;    
   */
   
endmodule