register.v

用verilog编写在FLEX10K上实现的简易CPU

//the general register
//	input 
//	output

module register(clk, rst, wt_en, reg_in, reg_out);
	input clk, rst, wt_en, reg_in;
	output reg_out;
	
	reg[15:0] reg_out;
	
	wire[15:0]	reg_in;
	
   	always@(posedge clk)
   	begin
   		if(rst)	
   			reg_out <= 16'b0000_0000_0000_0000;
   		else
   			if(wt_en)
   				reg_out <= reg_in;
   			else
   				reg_out <= reg_out;
   	end   
   	
endmodule