top.v.bak

用verilog编写在FLEX10K上实现的简易CPU

// top module

module top(clk, rst, alu_dm, dm_dr, pc_im, im_ir, dmrd_en, dmwt_en, imrd_en );
	input clk, rst, im_ir, dm_dr;
   output alu_dm, pc_im, dmrd_en, dmwt_en, imrd_en ;
   
	//------data--wire-------//
	// addr. from pc to im 
	wire[15:0] pc_im;
	
	// from im to ir 
	wire[15:0]	im_ir;
	
	// from ir to decoder 
	wire[15:0]	ir_decoder;
	
	//  addr. from decoder 
	//	to registers file and to imm_register
	wire[3:0]	de_addr1, de_addr2, de_addr3;
	wire[15:0]   de_imm;
		// to alu
	wire[7:0]	de_alu;
	
	//from register file to regiter
	wire[15:0]	rd_ar, rd_br;
	
	//from register to mutiplexer
	wire[15:0]	ar_mux, br_mux,
				//from decoder to reg_imm_mux
				imm_mux,
				//to data memory
				br_dm;
				
	// from mux to alu
	wire[15:0]	reg_zero_alu, reg_imm_alu;
	
	// from alu to dm and register file
	wire[15:0]	alu_dm;
	
	//from dm to dr
	wire[15:0]	dm_dr;
	//from dr to write back mux
	wire[15:0]	dr_mux;
	//from mux to register file
	wire[15:0]	mux_rgfl;
	
	//-------control--wire-------//
	
	//from decoder
	wire  reg_zero, reg_imm, reg_dm;
	wire[1:0]   op_type;
	
	//from control unit 
	wire 	ir_rd, 	//read instruction from ir
			ir_wt,	//write to ir
			a_in, b_in, //alu operand 
			rd1_en, rd2_en, wt3_en, //register file accession enable
			pc_en, 	//enable pc to be changed , add or jmp
			alu_en, //allow alu to compute
			de_en,  //decode instruction
			dmrd_en, //enable data memory to be read
			dmwt_en, //enable data memory to be writen
			imrd_en, //enable instruction memory to be read		
			dr_en;	//
				
				
	controlunit ctrlunt(rd1_en, rd2_en, wt3_en, pc_en, alu_en, de_en, ir_wt, a_in, b_in, dr_en,
				   dmrd_en, dmwt_en, imrd_en, clk, rst, op_type);
				
	//	input clk, rst, rd_en, wt_en, addr, data_in;
	//	output data_out;
	//memory 	instr_memo(.clk(clk), .rst(rst), .rd_en(imrd_en), .wt_en(imwt_en),
	//					.addr(pc_im), .data_in(16'h0000), .data_out(im_ir));
						
	//	input clk, rst, wt_en, reg_in;
	//	output reg_out;					
	register	ir(.clk(clk), .rst(rst), .wt_en(ir_wt), .reg_in(im_ir), .reg_out(ir_decoder));
	
	//	input  	ins, de_en;
	//	output  rgaddr1, rgaddr2, rgaddr3, imm, op, op_type, reg_zero, reg_imm, reg_dm;
	decoder	instr_decoder(.ins(ir_decoder), .de_en(de_en), .rgaddr1(de_addr1), .rgaddr2(de_addr2), .rgaddr3(de_addr3),
						  .imm(de_imm), .op(de_alu), .op_type(op_type), 
						  .reg_zero(reg_zero), .reg_imm(reg_imm), .reg_dm(reg_dm));
	
	//	input	clk, rst, rd1_en, rd2_en, wt3_en, rd1_addr, rd2_addr, wt3_addr, wt3_in;
	//	output	rd1_out, rd2_out;
	registerfile	general_register(.clk(clk), .rst(rst), .rd1_en(rd1_en), .rd2_en(rd2_en), .wt3_en(wt3_en), 
									 .rd1_addr(de_addr1), .rd2_addr(de_addr2), .wt3_addr(de_addr3), 
									 .wt3_in(mux_rgfl), .rd1_out(rd_ar), .rd2_out(rd_br) );
	
	register   	imm_r(.clk(clk), .rst(rst), .wt_en(1), .reg_in(de_imm), .reg_out(imm_mux));
	register 	ar(.clk(clk), .rst(rst), .wt_en(a_in), .reg_in(rd_ar), .reg_out(ar_mux));
	register	br(.clk(clk), .rst(rst), .wt_en(b_in), .reg_in(rd_br), .reg_out(br_mux));
	
	//	input control, data0, data1, clk;
	//	output out;
	mux2	reg_zero_mux(.control(reg_zero), .out(reg_zero_alu), .data0(ar_mux), .data1(16'h0000));
	mux2	reg_imm_mux(.control(reg_imm), .out(reg_imm_alu), .data0(br_mux), .data1(imm_mux));
	
	//	input clk, rst,  a_in, b_in, aluop, alu_en;
	//	output c_out;
	alu	 al_unit(.clk(clk), .rst(rst), .a_in(reg_zero_alu), .b_in(reg_imm_alu), .aluop(de_alu), .alu_en(alu_en),	            
	             .c_out(alu_dm) );
	
	mux2	reg_dm_mux(.control(reg_dm), .out(mux_rgfl), .data0(alu_dm), .data1(dr_mux));
	//	input clk, rst, rd_en, wt_en, addr, data_in;
	//	output data_out;
	//memory data_memo(.clk(clk), .rst(rst), .rd_en(dmrd_en), .wt_en(dmwt_en),
	//					.addr(alu_dm), .data_in(br_mux), .data_out(dm_dr));
	
	register dr(.clk(clk), .rst(rst), .wt_en(dr_en), .reg_in(dm_dr), .reg_out(dr_mux));
	
	//	input  addr_in, rst, clk, add_jmp, pc_en;
	//	 output  addr_out;
	programcounter pc(.addr_in(16'h0000), .rst(rst), .clk(clk), .add_jmp(1'b0), .pc_en(pc_en), .addr_out(pc_im));
	
					
endmodule