decoder.v

用verilog编写在FLEX10K上实现的简易CPU

// Instruction Decode

module decoder(ins, de_en, rgaddr1, rgaddr2, rgaddr3, imm, op, op_type, reg_zero, reg_imm, reg_dm);
	input  	ins, de_en;
	output  rgaddr1, rgaddr2, rgaddr3, imm, op, op_type, reg_zero, reg_imm, reg_dm;
	
	wire[15:0]	ins;
	wire[3:0]	rgaddr1, rgaddr2, rgaddr3;
	wire[15:0]	imm;
	wire[7:0]	op;
	wire[2:0]	op_type;
	
	
	parameter	st = 4'b0010,
				ld	= 4'b0011, 
				ist = 4'b0000,
				ild = 4'b0001;
	
	assign rgaddr1 = ins[7:4];
	assign rgaddr2 = ( (ins[15:12] == ist) || (ins[15:12] == st) )?
						ins[11:8] : ins[3:0];
	assign rgaddr3 = ( (ins[15:12] == ld) || (ins[15:12] == ild) )?
						ins[11:8] : ins[7:4];
	
	assign imm = ( (ins[15:13] == 3'b000) || (ins[15:14] == 2'b11) )?
						{12'h000, ins[3:0]} : {8'h00, ins[7:0]};
						
	assign op = ins[15]	? ins[15:8]	: 8'h00;   //000 as address addition
	
	assign op_type = ( (ins[15:12] == ist) || (ins[15:12] == st) ) ?
						2'b10 :	
						( ((ins[15:12] == ld) || (ins[15:12] == ild) )? 2'b11 : 2'b00 );
						
	assign reg_zero = (ins[15:12] == st) || (ins[15:12] == ld);
	assign reg_imm = (ins[15:14] == 2'b00) || (ins[15:14] == 2'b11 );
	assign reg_dm = (ins[15:12] == ld) || (ins[15:12] == ild);
	
endmodule