alu.v.bak

用verilog编写在FLEX10K上实现的简易CPU

//ALU
//file state:	UNCOMPILED
//		non-constant shift is not suppoted
module alu(clk, rst, a_in, b_in, aluop, c_out, alu_en);
	input clk, rst,  a_in, b_in, aluop, alu_en;
	output c_out;
	
	wire[3:0]	aluop;
	wire[15:0]	a_in, b_in;
	reg[15:0]	c_out;
	
	parameter 	add = 3'b000,
				sub = 3'b001,
				land= 3'b010,
				lor	= 3'b011,
				lxor= 3'b100,
				lnot= 3'b101,
				sll	= 3'b110,
				srl	= 3'b111;
	
	always@(posedge clk)
	begin
		if(rst)
			c_out <= 16'h0000;
			else
			if(alu_en)
				case(aluop)
				add	:	c_out <= a_in + b_in;
				sub	:	c_out <= a_in - b_in;
				land:	c_out <= a_in & b_in;
				lor	:	c_out <= a_in | b_in;	
				lxor:	c_out <= a_in ^ b_in;
				lnot:	c_out <= ~ a_in;
				sll	:	c_out <= a_in >> b_in;
				srl	:	c_out <= a_in << b_in;
				endcase
			else
			   c_out <= 16'hxxxx;
	end
endmodule