registerfile.v

用verilog编写在FLEX10K上实现的简易CPU

//UNCOMPILED!!!

//the general register files 
//access and modify must be authorified


module registerfile(clk, rst, rd1_en, rd2_en, wt3_en, rd1_addr, rd2_addr, wt3_addr,
					rd1_out, rd2_out, wt3_in);
	input	clk, rst, rd1_en, rd2_en, wt3_en, rd1_addr, rd2_addr, wt3_addr, wt3_in;
	output	rd1_out, rd2_out;
	
	wire[3:0]	rd1_addr, rd2_addr, wt3_addr;
	wire[15:0]   rd1_out, rd2_out, wt3_in;
	
	reg[15:0]	regfl[15:0];	//including 16 general registers
	
	integer regindex;

	assign rd1_out = ( rd1_en ) ? regfl[rd1_addr] : 16'hzzzz;
	assign rd2_out = ( rd2_en ) ? regfl[rd2_addr] : 16'hzzzz;
	
	always@(posedge clk)
	begin
		if(rst)
			for(regindex = 0; regindex < 16; regindex = regindex + 1)
				regfl[regindex] <= 16'b0000_0000_0000_0000;
		else
			if(wt3_en)
				regfl[wt3_addr] <= wt3_in;
	end
endmodule