stepper.tdf

来自「verilog编写实用多功能电子表」· TDF 代码 · 共 31 行

SUBDESIGN stepper
(
	clk, reset	: INPUT;
	ccw, cw		: INPUT;
	phase[3..0]	: OUTPUT;
)
VARIABLE
	ss: MACHINE OF BITS (phase[3..0])
		WITH STATES  (
			s0 = B"0001",
			s1 = B"0010",
			s2 = B"0100",
			s3 = B"1000");
BEGIN
	ss.clk   = clk;
	ss.reset = reset;

	TABLE
		ss,	ccw,	cw	=>	ss;

		s0,	1,		x	=>	s3;
		s0,	x,		1	=>	s1;
		s1,	1,		x	=>	s0;
		s1,	x,		1	=>	s2;
		s2,	1,		x	=>	s1;
		s2,	x,		1	=>	s3;
		s3,	1,		x	=>	s2;
		s3,	x,		1	=>	s0;
	END TABLE;
END;