ver_deci_poly_fir.html

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    <td><b><font color="#FFFFFF">Cycle of 4x Clock</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Coefficients to be Loaded</font></b></td>
  </tr>
  <tr> 
    <td valign="top"><b>1, 5&#133;&#133;</b></td>
    <td valign="top" align="center">h(0), h(4), h(8), h(12)</td>
  </tr>
  <tr> 
    <td valign="top"><b>2, 6&#133;&#133;</b></td>
    <td valign="top" align="center">h(3), h(7), h(11), h(15)</td>
  </tr>
  <tr> 
    <td valign="top"><b>3, 7&#133;&#133;</b></td>
    <td valign="top" align="center">h(2), h(6), h(10), h(14)</td>
  </tr>
  <tr> 
    <td valign="top"><b>4, 8&#133;&#133;</b></td>
    <td valign="top" align="center">h(1), h(5), h(9), h(13)</td>
  </tr>
</table>

<p>See <i><a href="/literature/an/an215.pdf">AN 215: Implementing High Performance DSP Functions in Stratix Devices</a></i> for details of the implementation.</p>

<p>Download the files used in this example:</p>
<ul>
<li><a href="/patches/examples/verilog/decimation_fir.zip">Download decimation_fir.zip</a>
<li><a href="../download/decimation_fir_vlog_readme-v1.0.0p1.txt">Download Polyphase Decimation FIR Filter Design Example README File</a>
</ul>

<p>Files in the download include:</p>

<ul>
<li>deci_poly.v - Top-level design file
<li>pll.v - Phase-locked loop (PLL) to generate 1x and 4x clock
<li>shift_reg.v - Shift register implemented using altshift_taps megafunction
<li>mult_add.v - Multiply-add function implemented using altmult_add megafunction
<li>accumulator.v - Accumulator implemented using lpm_add_sub megafunction
<li>rom0.v, rom1.v, rom2.v, rom3.v - ROM blocks to store filter coefficients
<li>rom1.mif, rom1.mif, rom2.mif, rom3.mif - Memory initialization file for filter coefficients
<li>deci_poly.m - MATLAB script to verify functionality of design
</ul>
<p>Figure 1 contains the deci_poly top-level block diagram.</p>


<p><b><i>Figure 1. deci_poly Top-Level Block Diagram</i></b></p>
<p><img src="images/ver-deci_poly_fir_fig1.gif" alt="Figure 1. deci_poly Top-Level Block Diagram" width="506" height="125" border="0"></p>

<p>Table 2 contains the polyphase decimation FIR filter example port listing.</p>
<br>
<table width="100%" border="1" cellspacing="0" cellpadding="2">
  <tr> 
    <td colspan="3"><b><i>Table 2. Polyphase Decimation FIR Filter Design Example 
      Port Listing</i></b></td>
  </tr>
  <tr bgcolor="#000099"> 
    <td><b><font color="#FFFFFF">Port Name</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Type</font></b></td>
    <td align="center"><b><font color="#FFFFFF">Description</font></b></td>
  </tr>
  <tr> 
    <td valign="top"><b>x0[8..0]</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Signed 9-bit input data is shifted in serially using the 
      shift register within the DSP block</td>
  </tr>
  <tr> 
    <td valign="top"><b>clk</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock</td>
  </tr>
  <tr> 
    <td valign="top"><b>clken</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Clock enable</td>
  </tr>
  <tr> 
    <td valign="top"><b>reset</b></td>
    <td valign="top" align="center">Input</td>
    <td valign="top">Reset</td>
  </tr>
  <tr> 
    <td valign="top"><b>load_data</b></td>
    <td valign="top" align="center">Output</td>
    <td valign="top">When asserted, the filter is ready to accept data on the 
      x0 port</td>
  </tr>
  <tr> 
    <td valign="top"><b>result[25..0]</b></td>
    <td valign="top" align="center">Output</td>
    <td valign="top">Output of the decimation FIR filter</td>
  </tr>
</table>
<br>
<HR noshade>
<p>For more information on using this example, go to:</p>
<ul><li><a href="verilog.html">How to Use Verilog HDL Examples</a>
<li><a href="/literature/an/an215.pdf"><i>AN 215: Implementing High Performance DSP Functions in Stratix Devices</i></a>
</ul>
<HR noshade>
<h2>Feedback</h2>

<p>Did this information help you?</p>

<p>If no, please log onto <a href="https://mysupport.altera.com/eservice/">mySupport</a> to file a technical request or enhancement.</p>

<p><hr noshade><p></p>

<font size="-1">Altera does not warrant that this solution will work for the customer's intended purpose and disclaims all liability for use of or reliance on the solution.</font>




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