_primary.vhd

SDRAM读写控制的实现与Modelsim仿真

library verilog;
use verilog.vl_types.all;
entity command is
    port(
        CLK             : in     vl_logic;
        RESET_N         : in     vl_logic;
        SADDR           : in     vl_logic_vector(21 downto 0);
        NOP             : in     vl_logic;
        READA           : in     vl_logic;
        WRITEA          : in     vl_logic;
        REFRESH         : in     vl_logic;
        PRECHARGE       : in     vl_logic;
        LOAD_MODE       : in     vl_logic;
        SC_CL           : in     vl_logic_vector(1 downto 0);
        SC_RC           : in     vl_logic_vector(1 downto 0);
        SC_RRD          : in     vl_logic_vector(3 downto 0);
        SC_PM           : in     vl_logic;
        SC_BL           : in     vl_logic_vector(3 downto 0);
        REF_REQ         : in     vl_logic;
        REF_ACK         : out    vl_logic;
        CM_ACK          : out    vl_logic;
        OE              : out    vl_logic_vector(1 downto 0);
        SA              : out    vl_logic_vector(11 downto 0);
        BA              : out    vl_logic_vector(1 downto 0);
        CS_N            : out    vl_logic;
        CKE             : out    vl_logic;
        RAS_N           : out    vl_logic;
        CAS_N           : out    vl_logic;
        WE_N            : out    vl_logic
    );
end command;