_primary.vhd

SDRAM读写控制的实现与Modelsim仿真

library verilog;
use verilog.vl_types.all;
entity test is
    generic(
        half_clk        : integer := 5;
        full_clk        : integer := 10
    );
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        data            : inout  vl_logic_vector(15 downto 0);
        addr            : out    vl_logic_vector(11 downto 0);
        ba              : out    vl_logic_vector(1 downto 0);
        sdclk           : out    vl_logic;
        cke             : out    vl_logic;
        cs_n            : out    vl_logic;
        ras_n           : out    vl_logic;
        cas_n           : out    vl_logic;
        we_n            : out    vl_logic;
        dqm             : out    vl_logic_vector(1 downto 0)
    );
end test;