_primary.vhd

SDRAM读写控制的实现与Modelsim仿真

library verilog;
use verilog.vl_types.all;
entity control_interface is
    port(
        CLK             : in     vl_logic;
        RESET_N         : in     vl_logic;
        CMD             : in     vl_logic_vector(2 downto 0);
        ADDR            : in     vl_logic_vector(21 downto 0);
        REF_ACK         : in     vl_logic;
        CM_ACK          : in     vl_logic;
        NOP             : out    vl_logic;
        READA           : out    vl_logic;
        WRITEA          : out    vl_logic;
        REFRESH         : out    vl_logic;
        PRECHARGE       : out    vl_logic;
        LOAD_MODE       : out    vl_logic;
        SADDR           : out    vl_logic_vector(21 downto 0);
        SC_CL           : out    vl_logic_vector(1 downto 0);
        SC_RC           : out    vl_logic_vector(1 downto 0);
        SC_RRD          : out    vl_logic_vector(3 downto 0);
        SC_PM           : out    vl_logic;
        SC_BL           : out    vl_logic_vector(3 downto 0);
        REF_REQ         : out    vl_logic;
        CMD_ACK         : out    vl_logic
    );
end control_interface;