_primary.vhd

SDRAM读写控制的实现与Modelsim仿真

library verilog;
use verilog.vl_types.all;
entity sdr_data_path is
    port(
        CLK             : in     vl_logic;
        RESET_N         : in     vl_logic;
        OE              : in     vl_logic_vector(1 downto 0);
        DATAIN          : in     vl_logic_vector(15 downto 0);
        DATAOUT         : out    vl_logic_vector(15 downto 0);
        DQIN            : in     vl_logic_vector(15 downto 0);
        DQOUT           : out    vl_logic_vector(15 downto 0)
    );
end sdr_data_path;