_primary.vhd

SDRAM读写控制的实现与Modelsim仿真

library verilog;
use verilog.vl_types.all;
entity sdram_test is
    generic(
        IDLE            : integer := 1;
        PRECHARGE       : integer := 2;
        PRECHARGE_ACK   : integer := 4;
        LOAD_MR         : integer := 8;
        LOAD_MR_ACK     : integer := 16;
        LOAD_R2         : integer := 32;
        LOAD_R2_ACK     : integer := 64;
        LOAD_R1         : integer := 128;
        IDLE_WR         : integer := 256;
        PAGE_WRITE      : integer := 512;
        BURST_WRITE     : integer := 1024;
        BT_W            : integer := 2048;
        WAIT_ACK_W_T    : integer := 4096;
        PAGE_READ       : integer := 8192;
        BURST_READ      : integer := 16384;
        BT              : integer := 32768;
        LAST_DATA       : integer := 65536;
        CLOSE_PAGE_W    : integer := 131072;
        REFRESH_W       : integer := 262144;
        CLOSE_PAGE_R    : integer := 524288;
        REFRESH_R       : integer := 1048576;
        RCD             : integer := 3;
        CL              : integer := 3;
        BL              : integer := 223;
        NOP             : integer := 0;
        READA           : integer := 1;
        WRITEA          : integer := 2;
        ARF             : integer := 3;
        PRECHRG         : integer := 4;
        LOAD_MODE       : integer := 5;
        LOAD_REG1       : integer := 6;
        LOAD_REG2       : integer := 7
    );
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        led             : out    vl_logic
    );
end sdram_test;