_primary.vhd

SDRAM读写控制的实现与Modelsim仿真

library verilog;
use verilog.vl_types.all;
entity mt48lc2m32b2 is
    generic(
        addr_bits       : integer := 11;
        data_bits       : integer := 32;
        col_bits        : integer := 8;
        mem_sizes       : integer := 524287;
        tAC             : real    := 5.500000;
        tHZ             : real    := 5.500000;
        tOH             : real    := 2.500000;
        tMRD            : real    := 2.000000;
        tRAS            : real    := 42.000000;
        tRC             : real    := 60.000000;
        tRCD            : real    := 20.000000;
        tRP             : real    := 20.000000;
        tRRD            : real    := 14.000000;
        tWRa            : real    := 7.000000;
        tWRp            : real    := 14.000000
    );
    port(
        Dq              : inout  vl_logic_vector;
        Addr            : in     vl_logic_vector;
        Ba              : in     vl_logic_vector(1 downto 0);
        Clk             : in     vl_logic;
        Cke             : in     vl_logic;
        Cs_n            : in     vl_logic;
        Ras_n           : in     vl_logic;
        Cas_n           : in     vl_logic;
        We_n            : in     vl_logic;
        Dqm             : in     vl_logic_vector(3 downto 0)
    );
end mt48lc2m32b2;