_primary.vhd

SDRAM读写控制的实现与Modelsim仿真

library verilog;
use verilog.vl_types.all;
entity sdr_sdram is
    port(
        CLK             : in     vl_logic;
        RESET_N         : in     vl_logic;
        ADDR            : in     vl_logic_vector(20 downto 0);
        CMD             : in     vl_logic_vector(2 downto 0);
        CMDACK          : out    vl_logic;
        DATAIN          : in     vl_logic_vector(31 downto 0);
        DATAOUT         : out    vl_logic_vector(31 downto 0);
        SA              : out    vl_logic_vector(11 downto 0);
        BA              : out    vl_logic_vector(1 downto 0);
        CS_N            : out    vl_logic;
        CKE             : out    vl_logic;
        RAS_N           : out    vl_logic;
        CAS_N           : out    vl_logic;
        WE_N            : out    vl_logic;
        DQ              : inout  vl_logic_vector(31 downto 0)
    );
end sdr_sdram;