test.spl

SDRAM读写控制的实现与Modelsim仿真

[Inputs]
clk
rst
[Outputs]
sdclk
cke
cs_n
ras_n
cas_n
we_n
=addr[11:0]=
=ba[1:0]=
=dqm[1:0]=
[BiDir]
=data[15:0]=
[ATTRIBUTES]
VeriModel test