test.syr

SDRAM读写控制的实现与Modelsim仿真

WARNING:Xst:638 - in unit test Conflict on KEEP property on signal Mtridata_dq<13> and Mtridata_dq<14> Mtridata_dq<14> signal will be lost.
WARNING:Xst:638 - in unit test Conflict on KEEP property on signal Mtridata_dq<13> and Mtridata_dq<4> Mtridata_dq<4> signal will be lost.
WARNING:Xst:638 - in unit test Conflict on KEEP property on signal Mtridata_dq<13> and Mtridata_dq<7> Mtridata_dq<7> signal will be lost.
WARNING:Xst:638 - in unit test Conflict on KEEP property on signal Mtridata_dq<13> and Mtridata_dq<8> Mtridata_dq<8> signal will be lost.
WARNING:Xst:638 - in unit test Conflict on KEEP property on signal Mtridata_dq<13> and Mtridata_dq<9> Mtridata_dq<9> signal will be lost.
WARNING:Xst:638 - in unit test Conflict on KEEP property on signal Mtridata_dq<13> and Mtridata_dq<10> Mtridata_dq<10> signal will be lost.
WARNING:Xst:638 - in unit test Conflict on KEEP property on signal Mtridata_dq<13> and Mtridata_dq<11> Mtridata_dq<11> signal will be lost.
WARNING:Xst:638 - in unit test Conflict on KEEP property on signal Mtridata_dq<13> and Mtridata_dq<12> Mtridata_dq<12> signal will be lost.

Optimizing unit <test> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Register <dqm_1> equivalent to <dqm_0> has been removed
Register <cs_n> equivalent to <dqm_0> has been removed
Found area constraint ratio of 100 (+ 5) on block test, actual ratio is 1.
FlipFlop state_cnt_0 has been replicated 3 time(s)
FlipFlop state_cnt_1 has been replicated 3 time(s)
FlipFlop state_cnt_2 has been replicated 4 time(s)
FlipFlop state_cnt_3 has been replicated 4 time(s)
FlipFlop state_cnt_4 has been replicated 4 time(s)
FlipFlop state_cnt_5 has been replicated 3 time(s)
FlipFlop dqm_0 has been replicated 2 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : test.ngr
Top Level Output File Name         : test
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 65

Macro Statistics :
# Registers                        : 25
#      1-bit register              : 22
#      12-bit register             : 1
#      16-bit register             : 1
#      2-bit register              : 1
# Counters                         : 1
#      6-bit up counter            : 1
# Tristates                        : 1
#      16-bit tristate buffer      : 1
# Comparators                      : 1
#      6-bit comparator greatequal : 1

Cell Usage :
# BELS                             : 110
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 4
#      LUT2_D                      : 3
#      LUT2_L                      : 4
#      LUT3                        : 5
#      LUT3_L                      : 8
#      LUT4                        : 21
#      LUT4_D                      : 1
#      LUT4_L                      : 39
#      MUXCY                       : 6
#      MUXF5                       : 9
#      MUXF6                       : 1
#      VCC                         : 1
#      XORCY                       : 6
# FlipFlops/Latches                : 65
#      FDC                         : 24
#      FDCE                        : 1
#      FDCPE                       : 27
#      FDP                         : 3
#      FDPE                        : 4
#      FDRE                        : 3
#      FDSE                        : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 64
#      IBUF                        : 1
#      IOBUF                       : 16
#      OBUF                        : 47
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      63  out of   3584     1%  
 Number of Slice Flip Flops:            65  out of   7168     0%  
 Number of 4 input LUTs:                85  out of   7168     1%  
 Number of bonded IOBs:                 65  out of    141    46%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 65    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.282ns (Maximum Frequency: 137.325MHz)
   Minimum input arrival time before clock: 1.825ns
   Maximum output required time after clock: 7.844ns
   Maximum combinational path delay: 8.093ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 7.282ns (frequency: 137.325MHz)
  Total number of paths / destination ports: 1195 / 62
-------------------------------------------------------------------------
Delay:               7.282ns (Levels of Logic = 4)
  Source:            state_cnt_1_1 (FF)
  Destination:       addr_10 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: state_cnt_1_1 to addr_10
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            7   0.720   1.261  state_cnt_1_1 (state_cnt_1_1)
     LUT4:I1->O            1   0.551   0.827  Ker6_SW0 (N63)
     LUT4:I3->O           13   0.551   1.170  _n00140 (CHOICE820)
     MUXF5:S->O            1   0.621   0.827  _n008388_SW31 (N509)
     LUT4_L:I3->LO         1   0.551   0.000  _n0008<0>43 (_n0008<0>)
     FDC:D                     0.203          addr_0
    ----------------------------------------
    Total                      7.282ns (3.197ns logic, 4.085ns route)
                                       (43.9% logic, 56.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              1.825ns (Levels of Logic = 1)
  Source:            data<0> (PAD)
  Destination:       data_out_0 (FF)
  Destination Clock: clk rising

  Data Path: data<0> to data_out_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           1   0.821   0.801  data_0_IOBUF (N471)
     FDC:D                     0.203          data_out_0
    ----------------------------------------
    Total                      1.825ns (1.024ns logic, 0.801ns route)
                                       (56.1% logic, 43.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 53 / 47
-------------------------------------------------------------------------
Offset:              7.844ns (Levels of Logic = 1)
  Source:            Mtrien_dq (FF)
  Destination:       data<0> (PAD)
  Source Clock:      clk rising

  Data Path: Mtrien_dq to data<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q            16   0.720   1.237  Mtrien_dq (Mtrien_dq)
     IOBUF:T->IO               5.887          data_14_IOBUF (data<14>)
    ----------------------------------------
    Total                      7.844ns (6.607ns logic, 1.237ns route)
                                       (84.2% logic, 15.8% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               8.093ns (Levels of Logic = 2)
  Source:            clk (PAD)
  Destination:       sdclk (PAD)

  Data Path: clk to sdclk
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     BUFGP:I->O           66   0.401   2.048  clk_BUFGP (sdclk_OBUF)
     OBUF:I->O                 5.644          sdclk_OBUF (sdclk)
    ----------------------------------------
    Total                      8.093ns (6.045ns logic, 2.048ns route)
                                       (74.7% logic, 25.3% route)

=========================================================================
CPU : 9.04 / 11.62 s | Elapsed : 9.00 / 11.00 s
 
--> 

Total memory usage is 102724 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   26 (   0 filtered)
Number of infos    :    2 (   0 filtered)