test.syr

SDRAM读写控制的实现与Modelsim仿真

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 2.29 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 2.29 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: test.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "test.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "test"
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : test
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : test.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "testtry.v"
Module <test> compiled
No errors in compilation
Analysis of file <"test.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <test>.
	hi_z = <u>ZZZZZZZZZZZZZZZZ
	half_clk = 5
	full_clk = 10
	testdata0 = 100
	testdata1 = 111
	Enabling task <nop>.
	Enabling task <precharge_all_bank>.
	Enabling task <nop>.
	Enabling task <auto_refresh>.
	Enabling task <nop>.
	Enabling task <auto_refresh>.
	Enabling task <nop>.
	Enabling task <load_mode_reg>.
	Enabling task <nop>.
	Enabling task <active>.
	Enabling task <nop>.
	Enabling task <write>.
	Enabling task <nop>.
	Enabling task <nop>.
	Enabling task <nop>.
	Enabling task <active>.
	Enabling task <nop>.
	Enabling task <write>.
	Enabling task <nop>.
	Enabling task <nop>.
	Enabling task <nop>.
	Enabling task <active>.
	Enabling task <nop>.
	Enabling task <read>.
	Enabling task <nop>.
	Enabling task <nop>.
	Enabling task <nop>.
WARNING:Xst:883 - "testtry.v" line 278: Ignored duplicate item in case statement. 
WARNING:Xst:883 - "testtry.v" line 284: Ignored duplicate item in case statement. 
Module <test> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <test>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================
INFO:Xst:1304 - Contents of register <ba> in unit <test> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <led> in unit <test> never changes during circuit operation. The register is replaced by logic.

Synthesizing Unit <test>.
    Related source file is "testtry.v".
WARNING:Xst:1778 - Inout <data> is assigned but never used.
    Found 1-bit register for signal <cs_n>.
    Found 12-bit register for signal <addr>.
    Found 1-bit register for signal <we_n>.
    Found 16-bit register for signal <data_out>.
    Found 1-bit register for signal <ras_n>.
    Found 2-bit register for signal <dqm>.
    Found 1-bit register for signal <cas_n>.
    Found 1-bit register for signal <cke>.
    Found 6-bit comparator greatequal for signal <$n0001> created at line 228.
    Found 16-bit tristate buffer for signal <dq>.
    Found 16-bit register for signal <Mtridata_dq>.
    Found 1-bit register for signal <Mtrien_dq>.
    Found 6-bit up counter for signal <state_cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred  36 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  16 Tristate(s).
Unit <test> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 6-bit up counter                  : 1
# Registers                        : 10
 1-bit register                    : 6
 12-bit register                   : 1
 16-bit register                   : 2
 2-bit register                    : 1
# Comparators                      : 1
 6-bit comparator greatequal       : 1
# Tristates                        : 1
 16-bit tristate buffer            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <addr_11> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <addr_2> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <addr_4> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <addr_8> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1710 - FF/Latch  <Mtridata_dq_13> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_dq_15> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_dq_14> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_dq_4> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_dq_7> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_dq_8> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_dq_9> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_dq_10> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_dq_11> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <Mtridata_dq_12> (without init value) has a constant value of 0 in block <test>.
WARNING:Xst:638 - in unit test Conflict on KEEP property on signal Mtridata_dq<13> and Mtridata_dq<15> Mtridata_dq<15> signal will be lost.