test.twr

SDRAM读写控制的实现与Modelsim仿真

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise d:\try\sdram\project\project.ise -intstyle ise
-e 3 -l 3 -s 4 -xml test test.ncd -o test.twr test.pcf


Design file:              test.ncd
Physical constraint file: test.pcf
Device,speed:             xc3s400,-4 (PRODUCTION 1.35 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
data<0>     |    2.851(R)|   -0.322(R)|sdclk_OBUF        |   0.000|
data<10>    |    0.845(R)|    0.769(R)|sdclk_OBUF        |   0.000|
data<11>    |    0.744(R)|    0.849(R)|sdclk_OBUF        |   0.000|
data<12>    |    0.845(R)|    0.769(R)|sdclk_OBUF        |   0.000|
data<13>    |    0.623(R)|    0.946(R)|sdclk_OBUF        |   0.000|
data<14>    |   -0.194(R)|    1.594(R)|sdclk_OBUF        |   0.000|
data<15>    |    0.643(R)|    0.931(R)|sdclk_OBUF        |   0.000|
data<1>     |    2.851(R)|   -0.322(R)|sdclk_OBUF        |   0.000|
data<2>     |    2.851(R)|   -0.322(R)|sdclk_OBUF        |   0.000|
data<3>     |    2.851(R)|   -0.322(R)|sdclk_OBUF        |   0.000|
data<4>     |    2.851(R)|   -0.322(R)|sdclk_OBUF        |   0.000|
data<5>     |    2.851(R)|   -0.322(R)|sdclk_OBUF        |   0.000|
data<6>     |    2.867(R)|   -0.341(R)|sdclk_OBUF        |   0.000|
data<7>     |    2.867(R)|   -0.341(R)|sdclk_OBUF        |   0.000|
data<8>     |    2.868(R)|   -0.341(R)|sdclk_OBUF        |   0.000|
data<9>     |    2.868(R)|   -0.341(R)|sdclk_OBUF        |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
addr<0>     |   10.449(R)|sdclk_OBUF        |   0.000|
addr<10>    |   10.393(R)|sdclk_OBUF        |   0.000|
addr<1>     |   10.654(R)|sdclk_OBUF        |   0.000|
addr<3>     |   10.322(R)|sdclk_OBUF        |   0.000|
addr<5>     |   10.077(R)|sdclk_OBUF        |   0.000|
addr<6>     |   10.586(R)|sdclk_OBUF        |   0.000|
addr<7>     |   10.125(R)|sdclk_OBUF        |   0.000|
addr<9>     |    9.717(R)|sdclk_OBUF        |   0.000|
cas_n       |   10.137(R)|sdclk_OBUF        |   0.000|
cke         |    7.383(R)|sdclk_OBUF        |   0.000|
cs_n        |    7.383(R)|sdclk_OBUF        |   0.000|
data<0>     |   11.159(R)|sdclk_OBUF        |   0.000|
data<10>    |   12.109(R)|sdclk_OBUF        |   0.000|
data<11>    |   12.249(R)|sdclk_OBUF        |   0.000|
data<12>    |   12.469(R)|sdclk_OBUF        |   0.000|
data<13>    |   12.111(R)|sdclk_OBUF        |   0.000|
data<14>    |   12.450(R)|sdclk_OBUF        |   0.000|
data<15>    |   12.588(R)|sdclk_OBUF        |   0.000|
data<1>     |   11.535(R)|sdclk_OBUF        |   0.000|
data<2>     |   11.524(R)|sdclk_OBUF        |   0.000|
data<3>     |   12.238(R)|sdclk_OBUF        |   0.000|
data<4>     |   11.178(R)|sdclk_OBUF        |   0.000|
data<5>     |   12.220(R)|sdclk_OBUF        |   0.000|
data<6>     |   11.084(R)|sdclk_OBUF        |   0.000|
data<7>     |   10.750(R)|sdclk_OBUF        |   0.000|
data<8>     |   11.444(R)|sdclk_OBUF        |   0.000|
data<9>     |   11.084(R)|sdclk_OBUF        |   0.000|
data_out<0> |    8.826(R)|sdclk_OBUF        |   0.000|
data_out<10>|    7.383(R)|sdclk_OBUF        |   0.000|
data_out<11>|    7.383(R)|sdclk_OBUF        |   0.000|
data_out<12>|    7.383(R)|sdclk_OBUF        |   0.000|
data_out<13>|    7.383(R)|sdclk_OBUF        |   0.000|
data_out<14>|    7.363(R)|sdclk_OBUF        |   0.000|
data_out<15>|    7.383(R)|sdclk_OBUF        |   0.000|
data_out<1> |    9.245(R)|sdclk_OBUF        |   0.000|
data_out<2> |    9.221(R)|sdclk_OBUF        |   0.000|
data_out<3> |    7.959(R)|sdclk_OBUF        |   0.000|
data_out<4> |    8.993(R)|sdclk_OBUF        |   0.000|
data_out<5> |    8.981(R)|sdclk_OBUF        |   0.000|
data_out<6> |   10.854(R)|sdclk_OBUF        |   0.000|
data_out<7> |    9.625(R)|sdclk_OBUF        |   0.000|
data_out<8> |   11.078(R)|sdclk_OBUF        |   0.000|
data_out<9> |    9.995(R)|sdclk_OBUF        |   0.000|
dqm<0>      |    7.383(R)|sdclk_OBUF        |   0.000|
dqm<1>      |    7.383(R)|sdclk_OBUF        |   0.000|
ras_n       |    9.787(R)|sdclk_OBUF        |   0.000|
we_n        |   10.074(R)|sdclk_OBUF        |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    8.547|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
clk            |sdclk          |   10.248|
---------------+---------------+---------+

Analysis completed Mon Oct 23 16:11:25 2006
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Peak Memory Usage: 87 MB