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📄 page_wr.v

📁 SDRAM读写控制的实现与Modelsim仿真
💻 V
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module test(clk,rst,
				data,addr,ba,
				sdclk,cke,
				cs_n,ras_n,cas_n,we_n,dqm,
				flash_ce,flash_oe,flash_rw,
				sram_ce,sram_oe,sram_we,sram_be
				);
				
input                 clk,rst          ;

inout   [15:0 ]       data             ;

output  [11:0 ]       addr             ;
output  [1 :0 ]       ba               ;
output                sdclk,cke        ;
output                cs_n,ras_n,cas_n,we_n   ;
output  [1 :0 ]       dqm              ;	
output                flash_ce,flash_oe,flash_rw ;
output                sram_ce,sram_oe,sram_we    ;
output  [1 :0 ]       sram_be          ;			

reg         [15 : 0] dq;                            // SDRAM I/O
reg         [11 : 0] addr;                          // SDRAM Address
reg         [1  : 0] ba;                            // Bank Address
//reg                  sdclk;                           // Clock
reg                  cke;                           // Synchronous Clock Enable
reg                  cs_n;                          // CS#
reg                  ras_n;                         // RAS#
reg                  cas_n;                         // CAS#
reg                  we_n;                          // WE#
reg          [1 : 0] dqm;                           // I/O Mask
 
reg         [6  :0 ] state_cnt         ;
wire        [15 : 0] data = dq;
wire                 sdclk = clk ;

wire   flash_ce = 1 ;
wire   flash_oe = 1 ;
wire   flash_rw = 1 ;
wire   sram_ce  = 1 ;
wire   sram_oe  = 1 ;
wire   sram_we  = 1 ;
wire  [1 :0 ] sram_be = 2'b11 ;

parameter            hi_z = 16'bz;                   // Hi-Z
parameter            half_clk =  5;
parameter            full_clk = 10;

task active;
    input          bank;
    input [11 : 0] row;
    input [15 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 1;
        we_n  = 1;
        dqm   = 0;
        ba    = bank;
        addr  = row;
        dq    = dq_in;
    end
endtask

task auto_refresh;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 0;
        we_n  = 1;
        dqm   = 0;
        ba    = 0;
        addr  = 0;
        dq    = hi_z;
    end
endtask

task burst_term;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 1;
        cas_n = 1;
        we_n  = 0;
        dqm   = 0;
        ba    = 0;
        addr  = 0;
        dq    = hi_z;
    end
endtask

task load_mode_reg;
    input [12 : 0] op_code;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 0;
        we_n  = 0;
        dqm   = 0;
        ba    = op_code [12 :11];
        addr  = op_code [10 : 0];
        dq    = hi_z;
    end
endtask

task nop;
    input  [1 : 0] dqm_in;
    input [15 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 1;
        cas_n = 1;
        we_n  = 1;
        dqm   = dqm_in;
        ba    = 0;
        addr  = 0;
        dq    = dq_in;
    end
endtask

task precharge_bank_0;
    input  [1 : 0] dqm_in;
    input [15 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 1;
        we_n  = 0;
        dqm   = dqm_in;
        ba    = 0;
        addr  = 0;
        dq    = dq_in;
    end
endtask

task precharge_bank_1;
    input  [1 : 0] dqm_in;
    input [15 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 1;
        we_n  = 0;
        dqm   = dqm_in;
        ba    = 1;
        addr  = 0;
        dq    = dq_in;
    end
endtask

task precharge_all_bank;
    input  [1 : 0] dqm_in;
    input [15 : 0] dq_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 0;
        cas_n = 1;
        we_n  = 0;
        dqm   = dqm_in;
        ba    = 0;
        addr  = 1024;            // A10 = 1
        dq    = dq_in;
    end
endtask

task read;
    input          bank;
    input [7  : 0] column;
    input [15 : 0] dq_in;
    input  [1 : 0] dqm_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 1;
        cas_n = 0;
        we_n  = 1;
        dqm   = dqm_in;
        ba    = bank;
        addr  = column;
        dq    = dq_in;
    end
endtask

task write;
    input          bank;
    input [7  : 0] column;
    input [15 : 0] dq_in;
    input  [1 : 0] dqm_in;
    begin
        cke   = 1;
        cs_n  = 0;
        ras_n = 1;
        cas_n = 0;
        we_n  = 0;
        dqm   = dqm_in;
        ba    = bank;
        addr  = column;
        dq    = dq_in;
    end
endtask

always @ ( posedge clk or negedge rst )
	if( !rst )
		begin
			state_cnt <= 6'b000_000 ;
		end
	else
		begin
			if( 6'b110_011 <= state_cnt )
				state_cnt <= 6'b000_000 ;
			else
				state_cnt <= state_cnt + 6'b000_001 ;
		end
		
always @ ( posedge clk or negedge rst )
	if( !rst )
		begin
			cke   = 0;     
			cs_n  = 1;     
		  ras_n = 1;     
		  cas_n = 1;     
		  we_n  = 1;     
		  dqm   = 3;
		  ba    = 0;  
		  addr  = 0;
		  dq    = hi_z; 
		end
	else
		begin
			case( state_cnt )
				'd1 : nop (0, hi_z);                     //1  Nop
        'd10: precharge_all_bank(0, hi_z);       //10 Precharge ALL Bank
        'd11: nop (0, hi_z);                     //11 Nop
        'd13: auto_refresh;                      //13 Auto Refresh
        'd14: nop (0, hi_z);                     //14 Nop
        'd22: auto_refresh;                      //22 Auto Refresh
        'd23: nop (0, hi_z);                     //23 Nop
        'd31: load_mode_reg (55);                //31 Load Mode: Lat = 3, BL = FULL, Seq
        'd32: nop (0, hi_z);                     //32 Nop
        'd33: active (0, 0, hi_z);               //33 Active: Bank = 0, Row = 0
        'd34: nop (0, hi_z);                     //34 Nop
        'd36: write  (0, 0, 100, 0);             //36 Write : Bank = 0, Col = 0, Dqm = 0
        'd37: nop (0, 101);                      //37 Nop
        'd38: nop (0, 102);                      //38 Nop
        'd39: nop (0, 103);                      //39 Nop
        'd40: nop (0, 104);                      //40 Nop
        'd41: nop (0, 105);                      //41 Nop
        'd42: nop (0, 106);                      //42 Nop
        'd43: burst_term;                        //43 Burst Terminate
        'd44: read(0, 0, hi_z, 0);               //44 Nop
        'd45: nop (0, hi_z);                     //45 Nop
        'd46: nop (0, hi_z);                     //46 Nop
        'd47: nop (0, hi_z);                     //47 Nop
        'd48: nop (0, hi_z);                     //48 Nop
        'd49: burst_term;                        //49 Nop
        'd50: nop (0, hi_z);                     //50 Nop        
      endcase
    end
    
endmodule

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