mul_4.vhd

VHDL语言实现的16位快速乘法器

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.MyFunc.ALL;
--USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.std_logic_signed.ALL;

Entity Mul_4 IS
	Port( clk   : In STD_LOGIC;
		  d1,d2 : IN STD_LOGIC_VECTOR(4 downto 1);
		  rst   : OUT STD_LOGIC_VECTOR(8 downto 1)
	);
End Entity Mul_4;

Architecture Pro of Mul_4 IS
signal dd1,dd2 : STD_LOGIC_VECTOR(4 downto 1);
signal result  : STD_LOGIC_VECTOR(8 downto 1);

Begin 
reg1: process(clk, d1)
begin
	if clk'Event and clk='1' then
	dd1<=d1;
	end if;
end process reg1;
reg2: process(clk,d1)
begin
	if clk'Event and clk='1' then
	dd2<=d2;
	end if;
end process reg2;

mul:process(clk)
	variable tmp1,tmp2 : STD_LOGIC_VECTOR(8 downto 1);
begin
if clk'Event and clk='1' then
	tmp1:=x"00";	tmp2:=x"00";
	if dd1(1)='1' then 
		tmp2(4 downto 1):= dd2(4 downto 1); 
	end if;
	
	tmp1:=x"00";
	if dd1(2)='1' then 
		tmp1(5 downto 2):= dd2(4 downto 1); 
		tmp2:=tmp2+tmp1;
	end if;

	tmp1:=x"00";
	if dd1(3)='1' then 
		tmp1(6 downto 3):= dd2(4 downto 1); 
		tmp2:=tmp2+tmp1;
	end if;

	tmp1:=x"00";
	if dd1(4)='1' then 
		tmp1(7 downto 4):= dd2(4 downto 1); 
		tmp2:=tmp2+tmp1;
	end if;
	rst<=tmp2;
end if;
end process mul;	
end Architecture pro;