mux_16.vhd

VHDL语言实现的16位快速乘法器

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_Arith.ALL;
Package SomeFunction Is
--	SUBTYPE  BIT8 IS STD_LOGIC_VECTOR(8 DOWNTO 1);
--	SUBTYPE  BIT4 IS STD_LOGIC_VECTOR(4 DOWNTO 1);
	Function "<<"(L:STD_LOGIC_VECTOR;R:Integer) return STD_LOGIC_VECTOR;
	Procedure SHL1(L:INOUT STD_LOGIC_VECTOR);
End Package SomeFunction;
Package body SomeFunction Is
	Procedure SHL1(L:INOUT STD_LOGIC_VECTOR) IS
--	variable temp : STD_LOGIC_VECTOR(32 downto 1);
	BEGIN 
		for i in 32 downto 2 loop
			L(i):=L(i-1);
		END loop; 
		L(1):='0';
	End SHL1;
	Function "<<"(L:STD_LOGIC_VECTOR;R:Integer) return STD_LOGIC_VECTOR IS
	Variable rst: STD_LOGIC_VECTOR(L'Range);
	variable n : INTEGER;	
	Begin 
		n:=L'Length-1;
		rst(n downto R+1):=L(n-R downto 1);
		return rst;
	End;
End SomeFunction;

Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_Arith.ALL;
Use IEEE.std_logic_signed.ALL;
Use Work.SomeFunction.ALL;
Entity Mux_16 Is
	Generic(BitNum : Integer :=16);
	Port(  IER : In STD_LOGIC_VECTOR(16 downto 1);
	       Faciend: In STD_LOGIC_VECTOR(16 downto 1);
		   DoMuxCtl :In	STD_LOGIC;
	       rst : Out STD_LOGIC_VECTOR(32 downto 1);
	       result : Out STD_LOGIC_VECTOR(32 downto 1)
		);
End Entity Mux_16;

Architecture Pro of Mux_16 IS
signal d1,d2 :STD_LOGIC_VECTOR(16 downto 1);
begin 

Process(IER)--DoMuxCtl,
begin 
--if DoMuxCtl'Event and DoMuxCtl='1' then 				
	d1<=IER;
--End if;	
end process;
Process(Faciend)--DoMuxCtl,
begin 
--if DoMuxCtl'Event and DoMuxCtl='1' then 	
	d2<=Faciend;
--End if;
end process;

DoMux: Process(DoMuxCtl)
			variable Temp1 : STD_LOGIC_VECTOR(32 downto 1);
			variable Temp2 : STD_LOGIC_VECTOR(32 downto 1);
	   Begin
			if DoMuxCtl'Event and DoMuxCtl='1' then 				
				Temp2:=X"00000000";
				Temp1(16 downto 1):=d1(16 downto 1);
				for i In 1 to 16 loop
					if d2(i)='1' then
						Temp2:=Temp1+Temp2;
					End if;
					SHL1(Temp1);
				end loop;
				result<=Temp2;
				rst<=Temp1;
			end if;
		End Process DoMux;
End pro;