mul_8.vhd

VHDL语言实现的16位快速乘法器

Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--USE WORK.MyFunc.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.std_logic_signed.ALL;

Entity Mul_4 IS
	Port( clk   : In STD_LOGIC;
		  d1,d2 : IN STD_LOGIC_VECTOR(4 downto 1);
		  rst   : OUT STD_LOGIC_VECTOR(8 downto 1)
	);
End Entity Mul_4;

Architecture Pro of Mul_4 IS
signal dd1,dd2 : STD_LOGIC_VECTOR(4 downto 1);
signal result  : STD_LOGIC_VECTOR(8 downto 1);

Begin 
reg1: process(clk, d1)
begin
	if clk'Event and clk='1' then
	dd1<=d1;
	end if;
end process reg1;
reg2: process(clk,d1)
begin
	if clk'Event and clk='1' then
	dd2<=d2;
	end if;
end process reg2;

mul:process(clk)
	variable tmp1,tmp2 : STD_LOGIC_VECTOR(8 downto 1);
begin
if clk'Event and clk='1' then
	tmp1:=x"00";	tmp2:=x"00";
	if dd1(1)='1' then 
		tmp2(4 downto 1):= dd2(4 downto 1); 
	end if;
	
	tmp1:=x"00";
	if dd1(2)='1' then 
		tmp1(5 downto 2):= dd2(4 downto 1); 
		tmp2:=tmp2+tmp1;
	end if;

	tmp1:=x"00";
	if dd1(3)='1' then 
		tmp1(6 downto 3):= dd2(4 downto 1); 
		tmp2:=tmp2+tmp1;
	end if;

	tmp1:=x"00";
	if dd1(4)='1' then 
		tmp1(7 downto 4):= dd2(4 downto 1); 
		tmp2:=tmp2+tmp1;
	end if;
	rst<=tmp2;
end if;
end process mul;	
end Architecture pro;
	
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.MyFunc.ALL;
Entity Mul_8 IS
	Generic(BitNum : Integer :=8);
	Port(  dd81 : In STD_LOGIC_VECTOR(8 downto 1);
	       dd82: In STD_LOGIC_VECTOR(8 downto 1);
		   clk8 :In	STD_LOGIC;
--	       rst : Out STD_LOGIC_VECTOR(32 downto 1);
	       rst16 : Out STD_LOGIC_VECTOR(16 downto 1)
		);
End Entity Mul_8 ;

Architecture Pro of Mul_8 IS
	COMPONENT Mul_4 
	Port( clk   : In STD_LOGIC;
		  d1,d2 : IN STD_LOGIC_VECTOR(4 downto 1);
		  rst   : OUT STD_LOGIC_VECTOR(8 downto 1)
	);
	END COMPONENT;
	SIGNAL IER1,IER2: STD_LOGIC_VECTOR(4 downto 1);
	SIGNAL FAC1,FAC2: STD_LOGIC_VECTOR(4 downto 1);
	SIGNAL rst11,rst12,rst21,rst22 :STD_LOGIC_VECTOR(8 downto 1);
	SIGNAL rst11_16,rst12_16,rst21_16,rst22_16 :STD_LOGIC_VECTOR(16 downto 1);
	SIGNAL rst1112,rst2122 :STD_LOGIC_VECTOR(16 downto 1);
Begin 

Process(clk8)
	if clk8'Event and clk8'Event then
	IER1(4 downto1)<=dd81(4 downto 1);
	End if;
End process;
Process(clk8)
	if clk8'Event and clk8'Event then
	IER2(4 downto1)<=dd81(8 downto 5);
	End if;
End process;
Process(clk8)
	if clk8'Event and clk8'Event then
	FAC1(4 downto1)<=dd82(4 downto 1);
	End if;
End process;
Process(clk8)
	if clk8'Event and clk8'Event then
	FAC2(4 downto1)<=dd83(8 downto 5);
	End if;
End process;

Mul11: Mul_4  Port Map(clk8,IER1,FAC1,rst11);
Mul12: Mul_4  Port Map(clk8,IER1,FAC2,rst12);
Mul21: Mul_4  Port Map(clk8,IER2,FAC1,rst21);
Mul22: Mul_4  Port Map(clk8,IER2,FAC2,rst22);

	rst11_16(8 downto 1);<=ret11(8 downto 1);
	rst12_16(8 downto 1);<=ret12(8 downto 1);	
	rst21_16(8 downto 1);<=ret21(8 downto 1);	
	rst22_16(8 downto 1);<=ret22(8 downto 1);
	rst1112 <= rst11_16 + rst12_16;
	rst2122 <= rst21_16 + rst22_16;
	rst16<=rst1112+rst2122;
	
	
End Architecture Pro;