cf_fp_mul_p_11_52.v

verilog浮点乘发器

endmodule

module cf_fp_mul_p_11_52_19 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [11:0] i8;
input  [88:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [11:0] o6;
output [52:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [11:0] n6;
reg    [87:0] n7;
wire   [11:0] s8_1;
wire   [87:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [11:0] s9_6;
wire   [52:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 12'b000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 12'b000000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 88'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 88'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_11_52_90 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_11_52_20 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_11_52_20 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [11:0] i8;
input  [87:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [11:0] o6;
output [52:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [11:0] n6;
reg    [86:0] n7;
wire   [11:0] s8_1;
wire   [86:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [11:0] s9_6;
wire   [52:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 12'b000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 12'b000000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 87'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 87'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_11_52_89 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_11_52_21 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_11_52_21 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [11:0] i8;
input  [86:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [11:0] o6;
output [52:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [11:0] n6;
reg    [85:0] n7;
wire   [11:0] s8_1;
wire   [85:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [11:0] s9_6;
wire   [52:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 12'b000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 12'b000000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 86'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 86'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_11_52_88 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_11_52_22 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_11_52_22 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [11:0] i8;
input  [85:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [11:0] o6;
output [52:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [11:0] n6;
reg    [84:0] n7;
wire   [11:0] s8_1;
wire   [84:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [11:0] s9_6;
wire   [52:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 12'b000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 12'b000000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 85'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 85'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_11_52_87 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_11_52_23 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_11_52_23 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [11:0] i8;
input  [84:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [11:0] o6;
output [52:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [11:0] n6;
reg    [83:0] n7;
wire   [11:0] s8_1;
wire   [83:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [11:0] s9_6;
wire   [52:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 12'b000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 12'b000000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 84'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 84'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_11_52_86 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_11_52_24 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_11_52_24 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [11:0] i8;
input  [83:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [11:0] o6;
output [52:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [11:0] n6;
reg    [82:0] n7;
wire   [11:0] s8_1;
wire   [82:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [11:0] s9_6;
wire   [52:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 12'b000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 12'b000000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 83'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 83'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_11_52_85 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_11_52_25 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_11_52_25 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  [11:0] i8;
input  [82:0] i9;
output o1;
output o2;
output o3;
output o4;
output o5;
output [11:0] o6;
output [52:0] o7;
reg    n1;
reg    n2;
reg    n3;
reg    n4;
reg    n5;
reg    [11:0] n6;
reg    [81:0] n7;
wire   [11:0] s8_1;
wire   [81:0] s8_2;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   [11:0] s9_6;
wire   [52:0] s9_7;
initial n1 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n1 <= 1'b0;
  else if (i1 == 1'b1)
    n1 <= i3;
initial n2 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n2 <= 1'b0;
  else if (i1 == 1'b1)
    n2 <= i4;
initial n3 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n3 <= 1'b0;
  else if (i1 == 1'b1)
    n3 <= i5;
initial n4 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n4 <= 1'b0;
  else if (i1 == 1'b1)
    n4 <= i6;
initial n5 = 1'b0;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n5 <= 1'b0;
  else if (i1 == 1'b1)
    n5 <= i7;
initial n6 = 12'b000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n6 <= 12'b000000000000;
  else if (i1 == 1'b1)
    n6 <= s8_1;
initial n7 = 82'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000;
always @ (posedge clock_c)
  if (i2 == 1'b1)
    n7 <= 82'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000;
  else if (i1 == 1'b1)
    n7 <= s8_2;
cf_fp_mul_p_11_52_84 s8 (i8, i9, s8_1, s8_2);
cf_fp_mul_p_11_52_26 s9 (clock_c, i1, i2, n1, n2, n3, n4, n5, n6, n7, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7);
assign o7 = s9_7;
assign o6 = s9_6;
assign o5 = s9_5;
assign o4 = s9_4;
assign o3 = s9_3;
assign o2 = s9_2;
assign o1 = s9_1;
endmodule

module cf_fp_mul_p_11_52_26 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, o1, o2, o3, o4, o5, o6, o7);
input  clock_c;
input  i1;