cf_fp_mul_p_11_52.vhd

verilog浮点乘发器

  i1(11 downto 11) &
  i1(10 downto 10) &
  i1(9 downto 9) &
  i1(8 downto 8) &
  i1(7 downto 7) &
  i1(6 downto 6) &
  i1(5 downto 5) &
  i1(4 downto 4) &
  i1(3 downto 3) &
  i1(2 downto 2) &
  i1(1 downto 1) &
  i1(0 downto 0);
n3 <= n2(19 downto 19);
n4 <= n2(18 downto 18) &
  n2(17 downto 17) &
  n2(16 downto 16) &
  n2(15 downto 15) &
  n2(14 downto 14) &
  n2(13 downto 13) &
  n2(12 downto 12) &
  n2(11 downto 11) &
  n2(10 downto 10) &
  n2(9 downto 9) &
  n2(8 downto 8) &
  n2(7 downto 7) &
  n2(6 downto 6) &
  n2(5 downto 5) &
  n2(4 downto 4) &
  n2(3 downto 3) &
  n2(2 downto 2) &
  n2(1 downto 1) &
  n2(0 downto 0);
n5 <= n4(18 downto 18);
n6 <= n4(17 downto 17) &
  n4(16 downto 16) &
  n4(15 downto 15) &
  n4(14 downto 14) &
  n4(13 downto 13) &
  n4(12 downto 12) &
  n4(11 downto 11) &
  n4(10 downto 10) &
  n4(9 downto 9) &
  n4(8 downto 8) &
  n4(7 downto 7) &
  n4(6 downto 6) &
  n4(5 downto 5) &
  n4(4 downto 4) &
  n4(3 downto 3) &
  n4(2 downto 2) &
  n4(1 downto 1) &
  n4(0 downto 0);
n7 <= n6(17 downto 17);
n8 <= n6(16 downto 16) &
  n6(15 downto 15) &
  n6(14 downto 14) &
  n6(13 downto 13) &
  n6(12 downto 12) &
  n6(11 downto 11) &
  n6(10 downto 10) &
  n6(9 downto 9) &
  n6(8 downto 8) &
  n6(7 downto 7) &
  n6(6 downto 6) &
  n6(5 downto 5) &
  n6(4 downto 4) &
  n6(3 downto 3) &
  n6(2 downto 2) &
  n6(1 downto 1) &
  n6(0 downto 0);
s9 : cf_fp_mul_p_11_52_125 port map (n8, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12, s9_13, s9_14, s9_15, s9_16, s9_17);
o21 <= s9_17;
o20 <= s9_16;
o19 <= s9_15;
o18 <= s9_14;
o17 <= s9_13;
o16 <= s9_12;
o15 <= s9_11;
o14 <= s9_10;
o13 <= s9_9;
o12 <= s9_8;
o11 <= s9_7;
o10 <= s9_6;
o9 <= s9_5;
o8 <= s9_4;
o7 <= s9_3;
o6 <= s9_2;
o5 <= s9_1;
o4 <= n7;
o3 <= n5;
o2 <= n3;
o1 <= n1;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_123 is
port (
i1 : in  unsigned(24 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0);
o6 : out unsigned(0 downto 0);
o7 : out unsigned(0 downto 0);
o8 : out unsigned(0 downto 0);
o9 : out unsigned(0 downto 0);
o10 : out unsigned(0 downto 0);
o11 : out unsigned(0 downto 0);
o12 : out unsigned(0 downto 0);
o13 : out unsigned(0 downto 0);
o14 : out unsigned(0 downto 0);
o15 : out unsigned(0 downto 0);
o16 : out unsigned(0 downto 0);
o17 : out unsigned(0 downto 0);
o18 : out unsigned(0 downto 0);
o19 : out unsigned(0 downto 0);
o20 : out unsigned(0 downto 0);
o21 : out unsigned(0 downto 0);
o22 : out unsigned(0 downto 0);
o23 : out unsigned(0 downto 0);
o24 : out unsigned(0 downto 0);
o25 : out unsigned(0 downto 0));
end entity cf_fp_mul_p_11_52_123;
architecture rtl of cf_fp_mul_p_11_52_123 is
signal n1 : unsigned(0 downto 0);
signal n2 : unsigned(23 downto 0);
signal n3 : unsigned(0 downto 0);
signal n4 : unsigned(22 downto 0);
signal n5 : unsigned(0 downto 0);
signal n6 : unsigned(21 downto 0);
signal n7 : unsigned(0 downto 0);
signal n8 : unsigned(20 downto 0);
signal s9_1 : unsigned(0 downto 0);
signal s9_2 : unsigned(0 downto 0);
signal s9_3 : unsigned(0 downto 0);
signal s9_4 : unsigned(0 downto 0);
signal s9_5 : unsigned(0 downto 0);
signal s9_6 : unsigned(0 downto 0);
signal s9_7 : unsigned(0 downto 0);
signal s9_8 : unsigned(0 downto 0);
signal s9_9 : unsigned(0 downto 0);
signal s9_10 : unsigned(0 downto 0);
signal s9_11 : unsigned(0 downto 0);
signal s9_12 : unsigned(0 downto 0);
signal s9_13 : unsigned(0 downto 0);
signal s9_14 : unsigned(0 downto 0);
signal s9_15 : unsigned(0 downto 0);
signal s9_16 : unsigned(0 downto 0);
signal s9_17 : unsigned(0 downto 0);
signal s9_18 : unsigned(0 downto 0);
signal s9_19 : unsigned(0 downto 0);
signal s9_20 : unsigned(0 downto 0);
signal s9_21 : unsigned(0 downto 0);
component cf_fp_mul_p_11_52_124 is
port (
i1 : in  unsigned(20 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0);
o6 : out unsigned(0 downto 0);
o7 : out unsigned(0 downto 0);
o8 : out unsigned(0 downto 0);
o9 : out unsigned(0 downto 0);
o10 : out unsigned(0 downto 0);
o11 : out unsigned(0 downto 0);
o12 : out unsigned(0 downto 0);
o13 : out unsigned(0 downto 0);
o14 : out unsigned(0 downto 0);
o15 : out unsigned(0 downto 0);
o16 : out unsigned(0 downto 0);
o17 : out unsigned(0 downto 0);
o18 : out unsigned(0 downto 0);
o19 : out unsigned(0 downto 0);
o20 : out unsigned(0 downto 0);
o21 : out unsigned(0 downto 0));
end component cf_fp_mul_p_11_52_124;
begin
n1 <= i1(24 downto 24);
n2 <= i1(23 downto 23) &
  i1(22 downto 22) &
  i1(21 downto 21) &
  i1(20 downto 20) &
  i1(19 downto 19) &
  i1(18 downto 18) &
  i1(17 downto 17) &
  i1(16 downto 16) &
  i1(15 downto 15) &
  i1(14 downto 14) &
  i1(13 downto 13) &
  i1(12 downto 12) &
  i1(11 downto 11) &
  i1(10 downto 10) &
  i1(9 downto 9) &
  i1(8 downto 8) &
  i1(7 downto 7) &
  i1(6 downto 6) &
  i1(5 downto 5) &
  i1(4 downto 4) &
  i1(3 downto 3) &
  i1(2 downto 2) &
  i1(1 downto 1) &
  i1(0 downto 0);
n3 <= n2(23 downto 23);
n4 <= n2(22 downto 22) &
  n2(21 downto 21) &
  n2(20 downto 20) &
  n2(19 downto 19) &
  n2(18 downto 18) &
  n2(17 downto 17) &
  n2(16 downto 16) &
  n2(15 downto 15) &
  n2(14 downto 14) &
  n2(13 downto 13) &
  n2(12 downto 12) &
  n2(11 downto 11) &
  n2(10 downto 10) &
  n2(9 downto 9) &
  n2(8 downto 8) &
  n2(7 downto 7) &
  n2(6 downto 6) &
  n2(5 downto 5) &
  n2(4 downto 4) &
  n2(3 downto 3) &
  n2(2 downto 2) &
  n2(1 downto 1) &
  n2(0 downto 0);
n5 <= n4(22 downto 22);
n6 <= n4(21 downto 21) &
  n4(20 downto 20) &
  n4(19 downto 19) &
  n4(18 downto 18) &
  n4(17 downto 17) &
  n4(16 downto 16) &
  n4(15 downto 15) &
  n4(14 downto 14) &
  n4(13 downto 13) &
  n4(12 downto 12) &
  n4(11 downto 11) &
  n4(10 downto 10) &
  n4(9 downto 9) &
  n4(8 downto 8) &
  n4(7 downto 7) &
  n4(6 downto 6) &
  n4(5 downto 5) &
  n4(4 downto 4) &
  n4(3 downto 3) &
  n4(2 downto 2) &
  n4(1 downto 1) &
  n4(0 downto 0);
n7 <= n6(21 downto 21);
n8 <= n6(20 downto 20) &
  n6(19 downto 19) &
  n6(18 downto 18) &
  n6(17 downto 17) &
  n6(16 downto 16) &
  n6(15 downto 15) &
  n6(14 downto 14) &
  n6(13 downto 13) &
  n6(12 downto 12) &
  n6(11 downto 11) &
  n6(10 downto 10) &
  n6(9 downto 9) &
  n6(8 downto 8) &
  n6(7 downto 7) &
  n6(6 downto 6) &
  n6(5 downto 5) &
  n6(4 downto 4) &
  n6(3 downto 3) &
  n6(2 downto 2) &
  n6(1 downto 1) &
  n6(0 downto 0);
s9 : cf_fp_mul_p_11_52_124 port map (n8, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12, s9_13, s9_14, s9_15, s9_16, s9_17, s9_18, s9_19, s9_20, s9_21);
o25 <= s9_21;
o24 <= s9_20;
o23 <= s9_19;
o22 <= s9_18;
o21 <= s9_17;
o20 <= s9_16;
o19 <= s9_15;
o18 <= s9_14;
o17 <= s9_13;
o16 <= s9_12;
o15 <= s9_11;
o14 <= s9_10;
o13 <= s9_9;
o12 <= s9_8;
o11 <= s9_7;
o10 <= s9_6;
o9 <= s9_5;
o8 <= s9_4;
o7 <= s9_3;
o6 <= s9_2;
o5 <= s9_1;
o4 <= n7;
o3 <= n5;
o2 <= n3;
o1 <= n1;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_122 is
port (
i1 : in  unsigned(28 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0);
o6 : out unsigned(0 downto 0);
o7 : out unsigned(0 downto 0);
o8 : out unsigned(0 downto 0);
o9 : out unsigned(0 downto 0);
o10 : out unsigned(0 downto 0);
o11 : out unsigned(0 downto 0);
o12 : out unsigned(0 downto 0);
o13 : out unsigned(0 downto 0);
o14 : out unsigned(0 downto 0);
o15 : out unsigned(0 downto 0);
o16 : out unsigned(0 downto 0);
o17 : out unsigned(0 downto 0);
o18 : out unsigned(0 downto 0);
o19 : out unsigned(0 downto 0);
o20 : out unsigned(0 downto 0);
o21 : out unsigned(0 downto 0);
o22 : out unsigned(0 downto 0);
o23 : out unsigned(0 downto 0);
o24 : out unsigned(0 downto 0);
o25 : out unsigned(0 downto 0);
o26 : out unsigned(0 downto 0);
o27 : out unsigned(0 downto 0);
o28 : out unsigned(0 downto 0);
o29 : out unsigned(0 downto 0));
end entity cf_fp_mul_p_11_52_122;
architecture rtl of cf_fp_mul_p_11_52_122 is
signal n1 : unsigned(0 downto 0);
signal n2 : unsigned(27 downto 0);
signal n3 : unsigned(0 downto 0);
signal n4 : unsigned(26 downto 0);
signal n5 : unsigned(0 downto 0);
signal n6 : unsigned(25 downto 0);
signal n7 : unsigned(0 downto 0);
signal n8 : unsigned(24 downto 0);
signal s9_1 : unsigned(0 downto 0);
signal s9_2 : unsigned(0 downto 0);
signal s9_3 : unsigned(0 downto 0);
signal s9_4 : unsigned(0 downto 0);
signal s9_5 : unsigned(0 downto 0);
signal s9_6 : unsigned(0 downto 0);
signal s9_7 : unsigned(0 downto 0);
signal s9_8 : unsigned(0 downto 0);
signal s9_9 : unsigned(0 downto 0);
signal s9_10 : unsigned(0 downto 0);
signal s9_11 : unsigned(0 downto 0);
signal s9_12 : unsigned(0 downto 0);
signal s9_13 : unsigned(0 downto 0);
signal s9_14 : unsigned(0 downto 0);
signal s9_15 : unsigned(0 downto 0);
signal s9_16 : unsigned(0 downto 0);
signal s9_17 : unsigned(0 downto 0);
signal s9_18 : unsigned(0 downto 0);
signal s9_19 : unsigned(0 downto 0);
signal s9_20 : unsigned(0 downto 0);
signal s9_21 : unsigned(0 downto 0);
signal s9_22 : unsigned(0 downto 0);
signal s9_23 : unsigned(0 downto 0);
signal s9_24 : unsigned(0 downto 0);
signal s9_25 : unsigned(0 downto 0);
component cf_fp_mul_p_11_52_123 is
port (
i1 : in  unsigned(24 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0);
o6 : out unsigned(0 downto 0);
o7 : out unsigned(0 downto 0);
o8 : out unsigned(0 downto 0);
o9 : out unsigned(0 downto 0);
o10 : out unsigned(0 downto 0);
o11 : out unsigned(0 downto 0);
o12 : out unsigned(0 downto 0);
o13 : out unsigned(0 downto 0);
o14 : out unsigned(0 downto 0);
o15 : out unsigned(0 downto 0);
o16 : out unsigned(0 downto 0);
o17 : out unsigned(0 downto 0);
o18 : out unsigned(0 downto 0);
o19 : out unsigned(0 downto 0);
o20 : out unsigned(0 downto 0);
o21 : out unsigned(0 downto 0);
o22 : out unsigned(0 downto 0);
o23 : out unsigned(0 downto 0);
o24 : out unsigned(0 downto 0);
o25 : out unsigned(0 downto 0));
end component cf_fp_mul_p_11_52_123;
begin
n1 <= i1(28 downto 28);
n2 <= i1(27 downto 27) &
  i1(26 downto 26) &
  i1(25 downto 25) &
  i1(24 downto 24) &
  i1(23 downto 23) &
  i1(22 downto 22) &
  i1(21 downto 21) &
  i1(20 downto 20) &
  i1(19 downto 19) &
  i1(18 downto 18) &
  i1(17 downto 17) &
  i1(16 downto 16) &
  i1(15 downto 15) &
  i1(14 downto 14) &
  i1(13 downto 13) &
  i1(12 downto 12) &
  i1(11 downto 11) &
  i1(10 downto 10) &
  i1(9 downto 9) &
  i1(8 downto 8) &
  i1(7 downto 7) &
  i1(6 downto 6) &
  i1(5 downto 5) &
  i1(4 downto 4) &
  i1(3 downto 3) &
  i1(2 downto 2) &
  i1(1 downto 1) &
  i1(0 downto 0);
n3 <= n2(27 downto 27);
n4 <= n2(26 downto 26) &
  n2(25 downto 25) &
  n2(24 downto 24) &
  n2(23 downto 23) &
  n2(22 downto 22) &
  n2(21 downto 21) &
  n2(20 downto 20) &
  n2(19 downto 19) &
  n2(18 downto 18) &
  n2(17 downto 17) &
  n2(16 downto 16) &
  n2(15 downto 15) &
  n2(14 downto 14) &
  n2(13 downto 13) &
  n2(12 downto 12) &
  n2(11 downto 11) &
  n2(10 downto 10) &
  n2(9 downto 9) &
  n2(8 downto 8) &
  n2(7 downto 7) &
  n2(6 downto 6) &
  n2(5 downto 5) &
  n2(4 downto 4) &
  n2(3 downto 3) &
  n2(2 downto 2) &
  n2(1 downto 1) &
  n2(0 downto 0);
n5 <= n4(26 downto 26);
n6 <= n4(25 downto 25) &
  n4(24 downto 24) &
  n4(23 downto 23) &
  n4(22 downto 22) &
  n4(21 downto 21) &
  n4(20 downto 20) &
  n4(19 downto 19) &
  n4(18 downto 18) &
  n4(17 downto 17) &
  n4(16 downto 16) &
  n4(15 downto 15) &
  n4(14 downto 14) &
  n4(13 downto 13) &
  n4(12 downto 12) &
  n4(11 downto 11) &
  n4(10 downto 10) &
  n4(9 downto 9) &
  n4(8 downto 8) &
  n4(7 downto 7) &
  n4(6 downto 6) &
  n4(5 downto 5) &
  n4(4 downto 4) &
  n4(3 downto 3) &
  n4(2 downto 2) &
  n4(1 downto 1) &
  n4(0 downto 0);
n7 <= n6(25 downto 25);
n8 <= n6(24 downto 24) &
  n6(23 downto 23) &
  n6(22 downto 22) &
  n6(21 downto 21) &
  n6(20 downto 20) &
  n6(19 downto 19) &
  n6(18 downto 18) &
  n6(17 downto 17) &
  n6(16 downto 16) &
  n6(15 downto 15) &
  n6(14 downto 14) &
  n6(13 downto 13) &
  n6(12 downto 12) &
  n6(11 downto 11) &
  n6(10 downto 10) &
  n6(9 downto 9) &
  n6(8 downto 8) &