cf_fp_mul_p_11_52.vhd

verilog浮点乘发器

o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0);
o6 : out unsigned(0 downto 0);
o7 : out unsigned(0 downto 0);
o8 : out unsigned(0 downto 0);
o9 : out unsigned(0 downto 0));
end entity cf_fp_mul_p_11_52_129;
architecture rtl of cf_fp_mul_p_11_52_129 is
signal n1 : unsigned(0 downto 0);
signal n2 : unsigned(7 downto 0);
signal n3 : unsigned(0 downto 0);
signal n4 : unsigned(6 downto 0);
signal n5 : unsigned(0 downto 0);
signal n6 : unsigned(5 downto 0);
signal n7 : unsigned(0 downto 0);
signal n8 : unsigned(4 downto 0);
signal s9_1 : unsigned(0 downto 0);
signal s9_2 : unsigned(0 downto 0);
signal s9_3 : unsigned(0 downto 0);
signal s9_4 : unsigned(0 downto 0);
signal s9_5 : unsigned(0 downto 0);
component cf_fp_mul_p_11_52_130 is
port (
i1 : in  unsigned(4 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0));
end component cf_fp_mul_p_11_52_130;
begin
n1 <= i1(8 downto 8);
n2 <= i1(7 downto 7) &
  i1(6 downto 6) &
  i1(5 downto 5) &
  i1(4 downto 4) &
  i1(3 downto 3) &
  i1(2 downto 2) &
  i1(1 downto 1) &
  i1(0 downto 0);
n3 <= n2(7 downto 7);
n4 <= n2(6 downto 6) &
  n2(5 downto 5) &
  n2(4 downto 4) &
  n2(3 downto 3) &
  n2(2 downto 2) &
  n2(1 downto 1) &
  n2(0 downto 0);
n5 <= n4(6 downto 6);
n6 <= n4(5 downto 5) &
  n4(4 downto 4) &
  n4(3 downto 3) &
  n4(2 downto 2) &
  n4(1 downto 1) &
  n4(0 downto 0);
n7 <= n6(5 downto 5);
n8 <= n6(4 downto 4) &
  n6(3 downto 3) &
  n6(2 downto 2) &
  n6(1 downto 1) &
  n6(0 downto 0);
s9 : cf_fp_mul_p_11_52_130 port map (n8, s9_1, s9_2, s9_3, s9_4, s9_5);
o9 <= s9_5;
o8 <= s9_4;
o7 <= s9_3;
o6 <= s9_2;
o5 <= s9_1;
o4 <= n7;
o3 <= n5;
o2 <= n3;
o1 <= n1;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_128 is
port (
i1 : in  unsigned(0 downto 0);
i2 : in  unsigned(0 downto 0);
i3 : in  unsigned(0 downto 0);
i4 : in  unsigned(0 downto 0);
i5 : in  unsigned(0 downto 0);
i6 : in  unsigned(0 downto 0);
i7 : in  unsigned(0 downto 0);
i8 : in  unsigned(0 downto 0);
i9 : in  unsigned(0 downto 0);
i10 : in  unsigned(0 downto 0);
i11 : in  unsigned(0 downto 0);
o1 : out unsigned(0 downto 0));
end entity cf_fp_mul_p_11_52_128;
architecture rtl of cf_fp_mul_p_11_52_128 is
signal n1 : unsigned(0 downto 0);
signal n2 : unsigned(0 downto 0);
signal n3 : unsigned(0 downto 0);
signal n4 : unsigned(0 downto 0);
signal n5 : unsigned(0 downto 0);
signal n6 : unsigned(0 downto 0);
signal n7 : unsigned(0 downto 0);
signal n8 : unsigned(0 downto 0);
signal n9 : unsigned(0 downto 0);
signal n10 : unsigned(0 downto 0);
begin
n1 <= i1 and i2;
n2 <= i3 and i4;
n3 <= i5 and i6;
n4 <= i7 and i8;
n5 <= i9 and i10;
n6 <= n1 and n2;
n7 <= n3 and n4;
n8 <= n5 and i11;
n9 <= n6 and n7;
n10 <= n9 and n8;
o1 <= n10;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_127 is
port (
i1 : in  unsigned(0 downto 0);
i2 : in  unsigned(0 downto 0);
i3 : in  unsigned(0 downto 0);
i4 : in  unsigned(0 downto 0);
i5 : in  unsigned(0 downto 0);
i6 : in  unsigned(0 downto 0);
i7 : in  unsigned(0 downto 0);
i8 : in  unsigned(0 downto 0);
i9 : in  unsigned(0 downto 0);
i10 : in  unsigned(0 downto 0);
i11 : in  unsigned(0 downto 0);
o1 : out unsigned(0 downto 0));
end entity cf_fp_mul_p_11_52_127;
architecture rtl of cf_fp_mul_p_11_52_127 is
signal n1 : unsigned(0 downto 0);
signal n2 : unsigned(0 downto 0);
signal n3 : unsigned(0 downto 0);
signal n4 : unsigned(0 downto 0);
signal n5 : unsigned(0 downto 0);
signal n6 : unsigned(0 downto 0);
signal n7 : unsigned(0 downto 0);
signal n8 : unsigned(0 downto 0);
signal n9 : unsigned(0 downto 0);
signal n10 : unsigned(0 downto 0);
begin
n1 <= i1 or i2;
n2 <= i3 or i4;
n3 <= i5 or i6;
n4 <= i7 or i8;
n5 <= i9 or i10;
n6 <= n1 or n2;
n7 <= n3 or n4;
n8 <= n5 or i11;
n9 <= n6 or n7;
n10 <= n9 or n8;
o1 <= n10;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_126 is
port (
i1 : in  unsigned(12 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0);
o6 : out unsigned(0 downto 0);
o7 : out unsigned(0 downto 0);
o8 : out unsigned(0 downto 0);
o9 : out unsigned(0 downto 0);
o10 : out unsigned(0 downto 0);
o11 : out unsigned(0 downto 0);
o12 : out unsigned(0 downto 0);
o13 : out unsigned(0 downto 0));
end entity cf_fp_mul_p_11_52_126;
architecture rtl of cf_fp_mul_p_11_52_126 is
signal n1 : unsigned(0 downto 0);
signal n2 : unsigned(11 downto 0);
signal n3 : unsigned(0 downto 0);
signal n4 : unsigned(10 downto 0);
signal n5 : unsigned(0 downto 0);
signal n6 : unsigned(9 downto 0);
signal n7 : unsigned(0 downto 0);
signal n8 : unsigned(8 downto 0);
signal s9_1 : unsigned(0 downto 0);
signal s9_2 : unsigned(0 downto 0);
signal s9_3 : unsigned(0 downto 0);
signal s9_4 : unsigned(0 downto 0);
signal s9_5 : unsigned(0 downto 0);
signal s9_6 : unsigned(0 downto 0);
signal s9_7 : unsigned(0 downto 0);
signal s9_8 : unsigned(0 downto 0);
signal s9_9 : unsigned(0 downto 0);
component cf_fp_mul_p_11_52_129 is
port (
i1 : in  unsigned(8 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0);
o6 : out unsigned(0 downto 0);
o7 : out unsigned(0 downto 0);
o8 : out unsigned(0 downto 0);
o9 : out unsigned(0 downto 0));
end component cf_fp_mul_p_11_52_129;
begin
n1 <= i1(12 downto 12);
n2 <= i1(11 downto 11) &
  i1(10 downto 10) &
  i1(9 downto 9) &
  i1(8 downto 8) &
  i1(7 downto 7) &
  i1(6 downto 6) &
  i1(5 downto 5) &
  i1(4 downto 4) &
  i1(3 downto 3) &
  i1(2 downto 2) &
  i1(1 downto 1) &
  i1(0 downto 0);
n3 <= n2(11 downto 11);
n4 <= n2(10 downto 10) &
  n2(9 downto 9) &
  n2(8 downto 8) &
  n2(7 downto 7) &
  n2(6 downto 6) &
  n2(5 downto 5) &
  n2(4 downto 4) &
  n2(3 downto 3) &
  n2(2 downto 2) &
  n2(1 downto 1) &
  n2(0 downto 0);
n5 <= n4(10 downto 10);
n6 <= n4(9 downto 9) &
  n4(8 downto 8) &
  n4(7 downto 7) &
  n4(6 downto 6) &
  n4(5 downto 5) &
  n4(4 downto 4) &
  n4(3 downto 3) &
  n4(2 downto 2) &
  n4(1 downto 1) &
  n4(0 downto 0);
n7 <= n6(9 downto 9);
n8 <= n6(8 downto 8) &
  n6(7 downto 7) &
  n6(6 downto 6) &
  n6(5 downto 5) &
  n6(4 downto 4) &
  n6(3 downto 3) &
  n6(2 downto 2) &
  n6(1 downto 1) &
  n6(0 downto 0);
s9 : cf_fp_mul_p_11_52_129 port map (n8, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9);
o13 <= s9_9;
o12 <= s9_8;
o11 <= s9_7;
o10 <= s9_6;
o9 <= s9_5;
o8 <= s9_4;
o7 <= s9_3;
o6 <= s9_2;
o5 <= s9_1;
o4 <= n7;
o3 <= n5;
o2 <= n3;
o1 <= n1;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_125 is
port (
i1 : in  unsigned(16 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0);
o6 : out unsigned(0 downto 0);
o7 : out unsigned(0 downto 0);
o8 : out unsigned(0 downto 0);
o9 : out unsigned(0 downto 0);
o10 : out unsigned(0 downto 0);
o11 : out unsigned(0 downto 0);
o12 : out unsigned(0 downto 0);
o13 : out unsigned(0 downto 0);
o14 : out unsigned(0 downto 0);
o15 : out unsigned(0 downto 0);
o16 : out unsigned(0 downto 0);
o17 : out unsigned(0 downto 0));
end entity cf_fp_mul_p_11_52_125;
architecture rtl of cf_fp_mul_p_11_52_125 is
signal n1 : unsigned(0 downto 0);
signal n2 : unsigned(15 downto 0);
signal n3 : unsigned(0 downto 0);
signal n4 : unsigned(14 downto 0);
signal n5 : unsigned(0 downto 0);
signal n6 : unsigned(13 downto 0);
signal n7 : unsigned(0 downto 0);
signal n8 : unsigned(12 downto 0);
signal s9_1 : unsigned(0 downto 0);
signal s9_2 : unsigned(0 downto 0);
signal s9_3 : unsigned(0 downto 0);
signal s9_4 : unsigned(0 downto 0);
signal s9_5 : unsigned(0 downto 0);
signal s9_6 : unsigned(0 downto 0);
signal s9_7 : unsigned(0 downto 0);
signal s9_8 : unsigned(0 downto 0);
signal s9_9 : unsigned(0 downto 0);
signal s9_10 : unsigned(0 downto 0);
signal s9_11 : unsigned(0 downto 0);
signal s9_12 : unsigned(0 downto 0);
signal s9_13 : unsigned(0 downto 0);
component cf_fp_mul_p_11_52_126 is
port (
i1 : in  unsigned(12 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0);
o6 : out unsigned(0 downto 0);
o7 : out unsigned(0 downto 0);
o8 : out unsigned(0 downto 0);
o9 : out unsigned(0 downto 0);
o10 : out unsigned(0 downto 0);
o11 : out unsigned(0 downto 0);
o12 : out unsigned(0 downto 0);
o13 : out unsigned(0 downto 0));
end component cf_fp_mul_p_11_52_126;
begin
n1 <= i1(16 downto 16);
n2 <= i1(15 downto 15) &
  i1(14 downto 14) &
  i1(13 downto 13) &
  i1(12 downto 12) &
  i1(11 downto 11) &
  i1(10 downto 10) &
  i1(9 downto 9) &
  i1(8 downto 8) &
  i1(7 downto 7) &
  i1(6 downto 6) &
  i1(5 downto 5) &
  i1(4 downto 4) &
  i1(3 downto 3) &
  i1(2 downto 2) &
  i1(1 downto 1) &
  i1(0 downto 0);
n3 <= n2(15 downto 15);
n4 <= n2(14 downto 14) &
  n2(13 downto 13) &
  n2(12 downto 12) &
  n2(11 downto 11) &
  n2(10 downto 10) &
  n2(9 downto 9) &
  n2(8 downto 8) &
  n2(7 downto 7) &
  n2(6 downto 6) &
  n2(5 downto 5) &
  n2(4 downto 4) &
  n2(3 downto 3) &
  n2(2 downto 2) &
  n2(1 downto 1) &
  n2(0 downto 0);
n5 <= n4(14 downto 14);
n6 <= n4(13 downto 13) &
  n4(12 downto 12) &
  n4(11 downto 11) &
  n4(10 downto 10) &
  n4(9 downto 9) &
  n4(8 downto 8) &
  n4(7 downto 7) &
  n4(6 downto 6) &
  n4(5 downto 5) &
  n4(4 downto 4) &
  n4(3 downto 3) &
  n4(2 downto 2) &
  n4(1 downto 1) &
  n4(0 downto 0);
n7 <= n6(13 downto 13);
n8 <= n6(12 downto 12) &
  n6(11 downto 11) &
  n6(10 downto 10) &
  n6(9 downto 9) &
  n6(8 downto 8) &
  n6(7 downto 7) &
  n6(6 downto 6) &
  n6(5 downto 5) &
  n6(4 downto 4) &
  n6(3 downto 3) &
  n6(2 downto 2) &
  n6(1 downto 1) &
  n6(0 downto 0);
s9 : cf_fp_mul_p_11_52_126 port map (n8, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12, s9_13);
o17 <= s9_13;
o16 <= s9_12;
o15 <= s9_11;
o14 <= s9_10;
o13 <= s9_9;
o12 <= s9_8;
o11 <= s9_7;
o10 <= s9_6;
o9 <= s9_5;
o8 <= s9_4;
o7 <= s9_3;
o6 <= s9_2;
o5 <= s9_1;
o4 <= n7;
o3 <= n5;
o2 <= n3;
o1 <= n1;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_124 is
port (
i1 : in  unsigned(20 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0);
o6 : out unsigned(0 downto 0);
o7 : out unsigned(0 downto 0);
o8 : out unsigned(0 downto 0);
o9 : out unsigned(0 downto 0);
o10 : out unsigned(0 downto 0);
o11 : out unsigned(0 downto 0);
o12 : out unsigned(0 downto 0);
o13 : out unsigned(0 downto 0);
o14 : out unsigned(0 downto 0);
o15 : out unsigned(0 downto 0);
o16 : out unsigned(0 downto 0);
o17 : out unsigned(0 downto 0);
o18 : out unsigned(0 downto 0);
o19 : out unsigned(0 downto 0);
o20 : out unsigned(0 downto 0);
o21 : out unsigned(0 downto 0));
end entity cf_fp_mul_p_11_52_124;
architecture rtl of cf_fp_mul_p_11_52_124 is
signal n1 : unsigned(0 downto 0);
signal n2 : unsigned(19 downto 0);
signal n3 : unsigned(0 downto 0);
signal n4 : unsigned(18 downto 0);
signal n5 : unsigned(0 downto 0);
signal n6 : unsigned(17 downto 0);
signal n7 : unsigned(0 downto 0);
signal n8 : unsigned(16 downto 0);
signal s9_1 : unsigned(0 downto 0);
signal s9_2 : unsigned(0 downto 0);
signal s9_3 : unsigned(0 downto 0);
signal s9_4 : unsigned(0 downto 0);
signal s9_5 : unsigned(0 downto 0);
signal s9_6 : unsigned(0 downto 0);
signal s9_7 : unsigned(0 downto 0);
signal s9_8 : unsigned(0 downto 0);
signal s9_9 : unsigned(0 downto 0);
signal s9_10 : unsigned(0 downto 0);
signal s9_11 : unsigned(0 downto 0);
signal s9_12 : unsigned(0 downto 0);
signal s9_13 : unsigned(0 downto 0);
signal s9_14 : unsigned(0 downto 0);
signal s9_15 : unsigned(0 downto 0);
signal s9_16 : unsigned(0 downto 0);
signal s9_17 : unsigned(0 downto 0);
component cf_fp_mul_p_11_52_125 is
port (
i1 : in  unsigned(16 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0);
o6 : out unsigned(0 downto 0);
o7 : out unsigned(0 downto 0);
o8 : out unsigned(0 downto 0);
o9 : out unsigned(0 downto 0);
o10 : out unsigned(0 downto 0);
o11 : out unsigned(0 downto 0);
o12 : out unsigned(0 downto 0);
o13 : out unsigned(0 downto 0);
o14 : out unsigned(0 downto 0);
o15 : out unsigned(0 downto 0);
o16 : out unsigned(0 downto 0);
o17 : out unsigned(0 downto 0));
end component cf_fp_mul_p_11_52_125;
begin
n1 <= i1(20 downto 20);
n2 <= i1(19 downto 19) &
  i1(18 downto 18) &
  i1(17 downto 17) &
  i1(16 downto 16) &
  i1(15 downto 15) &
  i1(14 downto 14) &
  i1(13 downto 13) &
  i1(12 downto 12) &