cf_fp_mul_p_11_52.vhd

verilog浮点乘发器

--
--  Copyright (c) 2003 Launchbird Design Systems, Inc.
--  All rights reserved.
--  
--  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
--    Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
--    Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
--  
--  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
--  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
--  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
--  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
--  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--  
--  
--  Overview:
--  
--    Performs floating point multiply.
--  
--  Interface:
--  
--    Synchronization:
--      clock_c  : Clock input.
--  
--    Inputs:
--      a_i : Left operand.
--      b_i : Right operand.
--  
--    Outputs:
--      x_o : Result.
--  
--  Built In Parameters:
--  
--    Exponent Precision = 11
--    Mantissa Precision = 52
--    Total    Precision = 64
--    Pipeline Latency   = 56 clock cycles
--  
--  
--  
--  
--  Generated by Confluence 0.6.3  --  Launchbird Design Systems, Inc.  --  www.launchbird.com
--  
--  Build Date : Fri Aug 22 09:47:38 CDT 2003
--  
--  Interface
--  
--    Build Name    : cf_fp_mul_p_11_52
--    Clock Domains : clock_c  
--    Vector Input  : a_i(64)
--    Vector Input  : b_i(64)
--    Vector Output : x_o(64)
--  
--  
--  

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_137 is
port (
i1 : in  unsigned(3 downto 0);
i2 : in  unsigned(2 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(2 downto 0);
o1 : out unsigned(2 downto 0));
end entity cf_fp_mul_p_11_52_137;
architecture rtl of cf_fp_mul_p_11_52_137 is
signal n1 : unsigned(3 downto 0);
signal n2 : unsigned(0 downto 0);
signal n3 : unsigned(3 downto 0);
signal n4 : unsigned(0 downto 0);
signal n5 : unsigned(3 downto 0);
signal n6 : unsigned(0 downto 0);
signal n7 : unsigned(2 downto 0);
signal n8 : unsigned(2 downto 0);
signal n9 : unsigned(2 downto 0);
begin
n1 <= "0010";
n2 <= "1" when i1 = n1 else "0";
n3 <= "0011";
n4 <= "1" when i1 = n3 else "0";
n5 <= "0001";
n6 <= "1" when i1 = n5 else "0";
n7 <= i3 when n6 = "1" else i2;
n8 <= i4 when n4 = "1" else n7;
n9 <= i4 when n2 = "1" else n8;
o1 <= n9;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_136 is
port (
i1 : in  unsigned(3 downto 0);
i2 : in  unsigned(2 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(2 downto 0);
i5 : in  unsigned(2 downto 0);
o1 : out unsigned(2 downto 0));
end entity cf_fp_mul_p_11_52_136;
architecture rtl of cf_fp_mul_p_11_52_136 is
signal n1 : unsigned(3 downto 0);
signal n2 : unsigned(0 downto 0);
signal n3 : unsigned(3 downto 0);
signal n4 : unsigned(0 downto 0);
signal n5 : unsigned(3 downto 0);
signal n6 : unsigned(0 downto 0);
signal n7 : unsigned(2 downto 0);
signal n8 : unsigned(2 downto 0);
signal n9 : unsigned(2 downto 0);
signal s10_1 : unsigned(2 downto 0);
component cf_fp_mul_p_11_52_137 is
port (
i1 : in  unsigned(3 downto 0);
i2 : in  unsigned(2 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(2 downto 0);
o1 : out unsigned(2 downto 0));
end component cf_fp_mul_p_11_52_137;
begin
n1 <= "0101";
n2 <= "1" when i1 = n1 else "0";
n3 <= "0110";
n4 <= "1" when i1 = n3 else "0";
n5 <= "0111";
n6 <= "1" when i1 = n5 else "0";
n7 <= i5 when n6 = "1" else s10_1;
n8 <= i5 when n4 = "1" else n7;
n9 <= i5 when n2 = "1" else n8;
s10 : cf_fp_mul_p_11_52_137 port map (i1, i2, i3, i4, s10_1);
o1 <= n9;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_135 is
port (
i1 : in  unsigned(3 downto 0);
i2 : in  unsigned(2 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(2 downto 0);
i5 : in  unsigned(2 downto 0);
i6 : in  unsigned(2 downto 0);
o1 : out unsigned(2 downto 0));
end entity cf_fp_mul_p_11_52_135;
architecture rtl of cf_fp_mul_p_11_52_135 is
signal n1 : unsigned(3 downto 0);
signal n2 : unsigned(0 downto 0);
signal n3 : unsigned(3 downto 0);
signal n4 : unsigned(0 downto 0);
signal n5 : unsigned(3 downto 0);
signal n6 : unsigned(0 downto 0);
signal n7 : unsigned(2 downto 0);
signal n8 : unsigned(2 downto 0);
signal n9 : unsigned(2 downto 0);
signal s10_1 : unsigned(2 downto 0);
component cf_fp_mul_p_11_52_136 is
port (
i1 : in  unsigned(3 downto 0);
i2 : in  unsigned(2 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(2 downto 0);
i5 : in  unsigned(2 downto 0);
o1 : out unsigned(2 downto 0));
end component cf_fp_mul_p_11_52_136;
begin
n1 <= "1110";
n2 <= "1" when i1 = n1 else "0";
n3 <= "1111";
n4 <= "1" when i1 = n3 else "0";
n5 <= "0100";
n6 <= "1" when i1 = n5 else "0";
n7 <= i5 when n6 = "1" else s10_1;
n8 <= i6 when n4 = "1" else n7;
n9 <= i6 when n2 = "1" else n8;
s10 : cf_fp_mul_p_11_52_136 port map (i1, i2, i3, i4, i5, s10_1);
o1 <= n9;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_134 is
port (
i1 : in  unsigned(3 downto 0);
i2 : in  unsigned(2 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(2 downto 0);
i5 : in  unsigned(2 downto 0);
i6 : in  unsigned(2 downto 0);
o1 : out unsigned(2 downto 0));
end entity cf_fp_mul_p_11_52_134;
architecture rtl of cf_fp_mul_p_11_52_134 is
signal n1 : unsigned(3 downto 0);
signal n2 : unsigned(0 downto 0);
signal n3 : unsigned(3 downto 0);
signal n4 : unsigned(0 downto 0);
signal n5 : unsigned(3 downto 0);
signal n6 : unsigned(0 downto 0);
signal n7 : unsigned(2 downto 0);
signal n8 : unsigned(2 downto 0);
signal n9 : unsigned(2 downto 0);
signal s10_1 : unsigned(2 downto 0);
component cf_fp_mul_p_11_52_135 is
port (
i1 : in  unsigned(3 downto 0);
i2 : in  unsigned(2 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(2 downto 0);
i5 : in  unsigned(2 downto 0);
i6 : in  unsigned(2 downto 0);
o1 : out unsigned(2 downto 0));
end component cf_fp_mul_p_11_52_135;
begin
n1 <= "1011";
n2 <= "1" when i1 = n1 else "0";
n3 <= "1100";
n4 <= "1" when i1 = n3 else "0";
n5 <= "1101";
n6 <= "1" when i1 = n5 else "0";
n7 <= i6 when n6 = "1" else s10_1;
n8 <= i6 when n4 = "1" else n7;
n9 <= i6 when n2 = "1" else n8;
s10 : cf_fp_mul_p_11_52_135 port map (i1, i2, i3, i4, i5, i6, s10_1);
o1 <= n9;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_133 is
port (
i1 : in  unsigned(3 downto 0);
i2 : in  unsigned(2 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(2 downto 0);
i5 : in  unsigned(2 downto 0);
i6 : in  unsigned(2 downto 0);
o1 : out unsigned(2 downto 0));
end entity cf_fp_mul_p_11_52_133;
architecture rtl of cf_fp_mul_p_11_52_133 is
signal n1 : unsigned(3 downto 0);
signal n2 : unsigned(0 downto 0);
signal n3 : unsigned(3 downto 0);
signal n4 : unsigned(0 downto 0);
signal n5 : unsigned(3 downto 0);
signal n6 : unsigned(0 downto 0);
signal n7 : unsigned(2 downto 0);
signal n8 : unsigned(2 downto 0);
signal n9 : unsigned(2 downto 0);
signal s10_1 : unsigned(2 downto 0);
component cf_fp_mul_p_11_52_134 is
port (
i1 : in  unsigned(3 downto 0);
i2 : in  unsigned(2 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(2 downto 0);
i5 : in  unsigned(2 downto 0);
i6 : in  unsigned(2 downto 0);
o1 : out unsigned(2 downto 0));
end component cf_fp_mul_p_11_52_134;
begin
n1 <= "1000";
n2 <= "1" when i1 = n1 else "0";
n3 <= "1001";
n4 <= "1" when i1 = n3 else "0";
n5 <= "1010";
n6 <= "1" when i1 = n5 else "0";
n7 <= i6 when n6 = "1" else s10_1;
n8 <= i6 when n4 = "1" else n7;
n9 <= i6 when n2 = "1" else n8;
s10 : cf_fp_mul_p_11_52_134 port map (i1, i2, i3, i4, i5, i6, s10_1);
o1 <= n9;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_132 is
port (
i1 : in  unsigned(62 downto 0);
i2 : in  unsigned(62 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(62 downto 0);
i5 : in  unsigned(62 downto 0);
i6 : in  unsigned(62 downto 0);
o1 : out unsigned(62 downto 0));
end entity cf_fp_mul_p_11_52_132;
architecture rtl of cf_fp_mul_p_11_52_132 is
signal n1 : unsigned(1 downto 0);
signal n2 : unsigned(0 downto 0);
signal n3 : unsigned(62 downto 0);
signal n4 : unsigned(62 downto 0);
signal n5 : unsigned(0 downto 0);
signal n6 : unsigned(0 downto 0);
signal n7 : unsigned(62 downto 0);
signal n8 : unsigned(0 downto 0);
signal n9 : unsigned(62 downto 0);
begin
n1 <= i3(2 downto 2) &
  i3(1 downto 1);
n2 <= i3(0 downto 0);
n3 <= i2 when n2 = "1" else i1;
n4 <= i5 when n2 = "1" else i4;
n5 <= n1(1 downto 1);
n6 <= n1(0 downto 0);
n7 <= n4 when n6 = "1" else n3;
n8 <= n5(0 downto 0);
n9 <= i6 when n8 = "1" else n7;
o1 <= n9;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_131 is
port (
i1 : in  unsigned(0 downto 0);
i2 : in  unsigned(0 downto 0);
i3 : in  unsigned(0 downto 0);
i4 : in  unsigned(0 downto 0);
i5 : in  unsigned(0 downto 0);
i6 : in  unsigned(11 downto 0);
i7 : in  unsigned(52 downto 0);
o1 : out unsigned(63 downto 0));
end entity cf_fp_mul_p_11_52_131;
architecture rtl of cf_fp_mul_p_11_52_131 is
signal n1 : unsigned(10 downto 0);
signal n2 : unsigned(51 downto 0);
signal n3 : unsigned(62 downto 0);
signal n4 : unsigned(62 downto 0);
signal n5 : unsigned(1 downto 0);
signal n6 : unsigned(2 downto 0);
signal n7 : unsigned(3 downto 0);
signal n8 : unsigned(2 downto 0);
signal n9 : unsigned(2 downto 0);
signal n10 : unsigned(2 downto 0);
signal n11 : unsigned(2 downto 0);
signal n12 : unsigned(2 downto 0);
signal n13 : unsigned(63 downto 0);
signal n14 : unsigned(62 downto 0);
signal n15 : unsigned(62 downto 0);
signal n16 : unsigned(62 downto 0);
signal s17_1 : unsigned(2 downto 0);
signal s18_1 : unsigned(62 downto 0);
component cf_fp_mul_p_11_52_133 is
port (
i1 : in  unsigned(3 downto 0);
i2 : in  unsigned(2 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(2 downto 0);
i5 : in  unsigned(2 downto 0);
i6 : in  unsigned(2 downto 0);
o1 : out unsigned(2 downto 0));
end component cf_fp_mul_p_11_52_133;
component cf_fp_mul_p_11_52_132 is
port (
i1 : in  unsigned(62 downto 0);
i2 : in  unsigned(62 downto 0);
i3 : in  unsigned(2 downto 0);
i4 : in  unsigned(62 downto 0);
i5 : in  unsigned(62 downto 0);
i6 : in  unsigned(62 downto 0);
o1 : out unsigned(62 downto 0));
end component cf_fp_mul_p_11_52_132;
begin
n1 <= i6(10 downto 10) &
  i6(9 downto 9) &
  i6(8 downto 8) &
  i6(7 downto 7) &
  i6(6 downto 6) &
  i6(5 downto 5) &
  i6(4 downto 4) &
  i6(3 downto 3) &
  i6(2 downto 2) &
  i6(1 downto 1) &
  i6(0 downto 0);
n2 <= i7(51 downto 51) &
  i7(50 downto 50) &
  i7(49 downto 49) &
  i7(48 downto 48) &
  i7(47 downto 47) &
  i7(46 downto 46) &
  i7(45 downto 45) &
  i7(44 downto 44) &
  i7(43 downto 43) &
  i7(42 downto 42) &
  i7(41 downto 41) &
  i7(40 downto 40) &
  i7(39 downto 39) &
  i7(38 downto 38) &
  i7(37 downto 37) &
  i7(36 downto 36) &
  i7(35 downto 35) &
  i7(34 downto 34) &
  i7(33 downto 33) &
  i7(32 downto 32) &
  i7(31 downto 31) &
  i7(30 downto 30) &
  i7(29 downto 29) &
  i7(28 downto 28) &
  i7(27 downto 27) &
  i7(26 downto 26) &
  i7(25 downto 25) &
  i7(24 downto 24) &
  i7(23 downto 23) &
  i7(22 downto 22) &
  i7(21 downto 21) &
  i7(20 downto 20) &
  i7(19 downto 19) &
  i7(18 downto 18) &
  i7(17 downto 17) &
  i7(16 downto 16) &
  i7(15 downto 15) &
  i7(14 downto 14) &
  i7(13 downto 13) &
  i7(12 downto 12) &
  i7(11 downto 11) &
  i7(10 downto 10) &
  i7(9 downto 9) &
  i7(8 downto 8) &
  i7(7 downto 7) &
  i7(6 downto 6) &
  i7(5 downto 5) &
  i7(4 downto 4) &
  i7(3 downto 3) &
  i7(2 downto 2) &
  i7(1 downto 1) &
  i7(0 downto 0);
n3 <= n1 & n2;
n4 <= "000000000000000000000000000000000000000000000000000000000000000";
n5 <= i3 & i4;
n6 <= i2 & n5;
n7 <= i1 & n6;
n8 <= "000";
n9 <= "001";
n10 <= "010";
n11 <= "011";
n12 <= "100";
n13 <= i5 & s18_1;
n14 <= "111111111110000000000000000000000000000000000000000000000000000";
n15 <= "111111111111111111111111111111111111111111111111111111111111111";
n16 <= "111111111110111111111111111111111111111111111111111111111111111";
s17 : cf_fp_mul_p_11_52_133 port map (n7, n8, n9, n10, n11, n12, s17_1);
s18 : cf_fp_mul_p_11_52_132 port map (n3, n4, s17_1, n14, n15, n16, s18_1);
o1 <= n13;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_130 is
port (
i1 : in  unsigned(4 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);
o3 : out unsigned(0 downto 0);
o4 : out unsigned(0 downto 0);
o5 : out unsigned(0 downto 0));
end entity cf_fp_mul_p_11_52_130;
architecture rtl of cf_fp_mul_p_11_52_130 is
signal n1 : unsigned(0 downto 0);
signal n2 : unsigned(3 downto 0);
signal n3 : unsigned(0 downto 0);
signal n4 : unsigned(2 downto 0);
signal n5 : unsigned(0 downto 0);
signal n6 : unsigned(1 downto 0);
signal n7 : unsigned(0 downto 0);
signal n8 : unsigned(0 downto 0);
signal n9 : unsigned(0 downto 0);
begin
n1 <= i1(4 downto 4);
n2 <= i1(3 downto 3) &
  i1(2 downto 2) &
  i1(1 downto 1) &
  i1(0 downto 0);
n3 <= n2(3 downto 3);
n4 <= n2(2 downto 2) &
  n2(1 downto 1) &
  n2(0 downto 0);
n5 <= n4(2 downto 2);
n6 <= n4(1 downto 1) &
  n4(0 downto 0);
n7 <= n6(1 downto 1);
n8 <= n6(0 downto 0);
n9 <= n8(0 downto 0);
o5 <= n9;
o4 <= n7;
o3 <= n5;
o2 <= n3;
o1 <= n1;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cf_fp_mul_p_11_52_129 is
port (
i1 : in  unsigned(8 downto 0);
o1 : out unsigned(0 downto 0);
o2 : out unsigned(0 downto 0);