cf_fp_mul_c_11_52.v

verilog浮点乘发器

  n4[2],
  n4[1],
  n4[0]};
assign n7 = n6[9];
assign n8 = {n6[8],
  n6[7],
  n6[6],
  n6[5],
  n6[4],
  n6[3],
  n6[2],
  n6[1],
  n6[0]};
cf_fp_mul_c_11_52_90 s9 (n8, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9);
assign o13 = s9_9;
assign o12 = s9_8;
assign o11 = s9_7;
assign o10 = s9_6;
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n7;
assign o3 = n5;
assign o2 = n3;
assign o1 = n1;
endmodule

module cf_fp_mul_c_11_52_20 (i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, o1);
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  i8;
input  i9;
input  i10;
input  i11;
output o1;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   n5;
wire   n6;
wire   n7;
wire   n8;
wire   n9;
wire   n10;
assign n1 = i1 | i2;
assign n2 = i3 | i4;
assign n3 = i5 | i6;
assign n4 = i7 | i8;
assign n5 = i9 | i10;
assign n6 = n1 | n2;
assign n7 = n3 | n4;
assign n8 = n5 | i11;
assign n9 = n6 | n7;
assign n10 = n9 | n8;
assign o1 = n10;
endmodule

module cf_fp_mul_c_11_52_21 (i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, o1);
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  i8;
input  i9;
input  i10;
input  i11;
output o1;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   n5;
wire   n6;
wire   n7;
wire   n8;
wire   n9;
wire   n10;
assign n1 = i1 & i2;
assign n2 = i3 & i4;
assign n3 = i5 & i6;
assign n4 = i7 & i8;
assign n5 = i9 & i10;
assign n6 = n1 & n2;
assign n7 = n3 & n4;
assign n8 = n5 & i11;
assign n9 = n6 & n7;
assign n10 = n9 & n8;
assign o1 = n10;
endmodule

module cf_fp_mul_c_11_52_22 (i1, i2, i3, i4, i5, i6, i7, o1);
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  [11:0] i6;
input  [52:0] i7;
output [63:0] o1;
wire   [10:0] n1;
wire   [51:0] n2;
wire   [62:0] n3;
wire   [62:0] n4;
wire   [1:0] n5;
wire   [2:0] n6;
wire   [3:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
wire   [2:0] n10;
wire   [2:0] n11;
wire   [2:0] n12;
wire   [63:0] n13;
wire   [62:0] n14;
wire   [62:0] n15;
wire   [62:0] n16;
wire   [2:0] s17_1;
wire   [62:0] s18_1;
assign n1 = {i6[10],
  i6[9],
  i6[8],
  i6[7],
  i6[6],
  i6[5],
  i6[4],
  i6[3],
  i6[2],
  i6[1],
  i6[0]};
assign n2 = {i7[51],
  i7[50],
  i7[49],
  i7[48],
  i7[47],
  i7[46],
  i7[45],
  i7[44],
  i7[43],
  i7[42],
  i7[41],
  i7[40],
  i7[39],
  i7[38],
  i7[37],
  i7[36],
  i7[35],
  i7[34],
  i7[33],
  i7[32],
  i7[31],
  i7[30],
  i7[29],
  i7[28],
  i7[27],
  i7[26],
  i7[25],
  i7[24],
  i7[23],
  i7[22],
  i7[21],
  i7[20],
  i7[19],
  i7[18],
  i7[17],
  i7[16],
  i7[15],
  i7[14],
  i7[13],
  i7[12],
  i7[11],
  i7[10],
  i7[9],
  i7[8],
  i7[7],
  i7[6],
  i7[5],
  i7[4],
  i7[3],
  i7[2],
  i7[1],
  i7[0]};
assign n3 = {n1, n2};
assign n4 = 63'b000000000000000000000000000000000000000000000000000000000000000;
assign n5 = {i3, i4};
assign n6 = {i2, n5};
assign n7 = {i1, n6};
assign n8 = 3'b000;
assign n9 = 3'b001;
assign n10 = 3'b010;
assign n11 = 3'b011;
assign n12 = 3'b100;
assign n13 = {i5, s18_1};
assign n14 = 63'b111111111110000000000000000000000000000000000000000000000000000;
assign n15 = 63'b111111111111111111111111111111111111111111111111111111111111111;
assign n16 = 63'b111111111110111111111111111111111111111111111111111111111111111;
cf_fp_mul_c_11_52_24 s17 (n7, n8, n9, n10, n11, n12, s17_1);
cf_fp_mul_c_11_52_23 s18 (n3, n4, s17_1, n14, n15, n16, s18_1);
assign o1 = n13;
endmodule

module cf_fp_mul_c_11_52_23 (i1, i2, i3, i4, i5, i6, o1);
input  [62:0] i1;
input  [62:0] i2;
input  [2:0] i3;
input  [62:0] i4;
input  [62:0] i5;
input  [62:0] i6;
output [62:0] o1;
wire   [1:0] n1;
wire   n2;
wire   [62:0] n3;
wire   [62:0] n4;
wire   n5;
wire   n6;
wire   [62:0] n7;
wire   n8;
wire   [62:0] n9;
assign n1 = {i3[2],
  i3[1]};
assign n2 = i3[0];
assign n3 = n2 ? i2 : i1;
assign n4 = n2 ? i5 : i4;
assign n5 = n1[1];
assign n6 = n1[0];
assign n7 = n6 ? n4 : n3;
assign n8 = n5;
assign n9 = n8 ? i6 : n7;
assign o1 = n9;
endmodule

module cf_fp_mul_c_11_52_24 (i1, i2, i3, i4, i5, i6, o1);
input  [3:0] i1;
input  [2:0] i2;
input  [2:0] i3;
input  [2:0] i4;
input  [2:0] i5;
input  [2:0] i6;
output [2:0] o1;
wire   [3:0] n1;
wire   n2;
wire   [3:0] n3;
wire   n4;
wire   [3:0] n5;
wire   n6;
wire   [2:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
wire   [2:0] s10_1;
assign n1 = 4'b1000;
assign n2 = i1 == n1;
assign n3 = 4'b1001;
assign n4 = i1 == n3;
assign n5 = 4'b1010;
assign n6 = i1 == n5;
assign n7 = n6 ? i6 : s10_1;
assign n8 = n4 ? i6 : n7;
assign n9 = n2 ? i6 : n8;
cf_fp_mul_c_11_52_25 s10 (i1, i2, i3, i4, i5, i6, s10_1);
assign o1 = n9;
endmodule

module cf_fp_mul_c_11_52_25 (i1, i2, i3, i4, i5, i6, o1);
input  [3:0] i1;
input  [2:0] i2;
input  [2:0] i3;
input  [2:0] i4;
input  [2:0] i5;
input  [2:0] i6;
output [2:0] o1;
wire   [3:0] n1;
wire   n2;
wire   [3:0] n3;
wire   n4;
wire   [3:0] n5;
wire   n6;
wire   [2:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
wire   [2:0] s10_1;
assign n1 = 4'b1011;
assign n2 = i1 == n1;
assign n3 = 4'b1100;
assign n4 = i1 == n3;
assign n5 = 4'b1101;
assign n6 = i1 == n5;
assign n7 = n6 ? i6 : s10_1;
assign n8 = n4 ? i6 : n7;
assign n9 = n2 ? i6 : n8;
cf_fp_mul_c_11_52_26 s10 (i1, i2, i3, i4, i5, i6, s10_1);
assign o1 = n9;
endmodule

module cf_fp_mul_c_11_52_26 (i1, i2, i3, i4, i5, i6, o1);
input  [3:0] i1;
input  [2:0] i2;
input  [2:0] i3;
input  [2:0] i4;
input  [2:0] i5;
input  [2:0] i6;
output [2:0] o1;
wire   [3:0] n1;
wire   n2;
wire   [3:0] n3;
wire   n4;
wire   [3:0] n5;
wire   n6;
wire   [2:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
wire   [2:0] s10_1;
assign n1 = 4'b1110;
assign n2 = i1 == n1;
assign n3 = 4'b1111;
assign n4 = i1 == n3;
assign n5 = 4'b0100;
assign n6 = i1 == n5;
assign n7 = n6 ? i5 : s10_1;
assign n8 = n4 ? i6 : n7;
assign n9 = n2 ? i6 : n8;
cf_fp_mul_c_11_52_27 s10 (i1, i2, i3, i4, i5, s10_1);
assign o1 = n9;
endmodule

module cf_fp_mul_c_11_52_27 (i1, i2, i3, i4, i5, o1);
input  [3:0] i1;
input  [2:0] i2;
input  [2:0] i3;
input  [2:0] i4;
input  [2:0] i5;
output [2:0] o1;
wire   [3:0] n1;
wire   n2;
wire   [3:0] n3;
wire   n4;
wire   [3:0] n5;
wire   n6;
wire   [2:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
wire   [2:0] s10_1;
assign n1 = 4'b0101;
assign n2 = i1 == n1;
assign n3 = 4'b0110;
assign n4 = i1 == n3;
assign n5 = 4'b0111;
assign n6 = i1 == n5;
assign n7 = n6 ? i5 : s10_1;
assign n8 = n4 ? i5 : n7;
assign n9 = n2 ? i5 : n8;
cf_fp_mul_c_11_52_28 s10 (i1, i2, i3, i4, s10_1);
assign o1 = n9;
endmodule

module cf_fp_mul_c_11_52_28 (i1, i2, i3, i4, o1);
input  [3:0] i1;
input  [2:0] i2;
input  [2:0] i3;
input  [2:0] i4;
output [2:0] o1;
wire   [3:0] n1;
wire   n2;
wire   [3:0] n3;
wire   n4;
wire   [3:0] n5;
wire   n6;
wire   [2:0] n7;
wire   [2:0] n8;
wire   [2:0] n9;
assign n1 = 4'b0010;
assign n2 = i1 == n1;
assign n3 = 4'b0011;
assign n4 = i1 == n3;
assign n5 = 4'b0001;
assign n6 = i1 == n5;
assign n7 = n6 ? i3 : i2;
assign n8 = n4 ? i4 : n7;
assign n9 = n2 ? i4 : n8;
assign o1 = n9;
endmodule

module cf_fp_mul_c_11_52_29 (i1, i2, o1, o2);
input  [11:0] i1;
input  [104:0] i2;
output [11:0] o1;
output [103:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [11:0] n4;
wire   [11:0] n5;
wire   [11:0] n6;
wire   [103:0] n7;
wire   [103:0] n8;
wire   [103:0] n9;
wire   s10_1;
assign n1 = i2[104];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 12'b000000000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[103],
  i2[102],
  i2[101],
  i2[100],
  i2[99],
  i2[98],
  i2[97],
  i2[96],
  i2[95],
  i2[94],
  i2[93],
  i2[92],
  i2[91],
  i2[90],
  i2[89],
  i2[88],
  i2[87],
  i2[86],
  i2[85],
  i2[84],
  i2[83],
  i2[82],
  i2[81],
  i2[80],
  i2[79],
  i2[78],
  i2[77],
  i2[76],
  i2[75],
  i2[74],
  i2[73],
  i2[72],
  i2[71],
  i2[70],
  i2[69],
  i2[68],
  i2[67],
  i2[66],
  i2[65],
  i2[64],
  i2[63],
  i2[62],
  i2[61],
  i2[60],
  i2[59],
  i2[58],
  i2[57],
  i2[56],
  i2[55],
  i2[54],
  i2[53],
  i2[52],
  i2[51],
  i2[50],
  i2[49],
  i2[48],
  i2[47],
  i2[46],
  i2[45],
  i2[44],
  i2[43],
  i2[42],
  i2[41],
  i2[40],
  i2[39],
  i2[38],
  i2[37],
  i2[36],
  i2[35],
  i2[34],
  i2[33],
  i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[104],
  i2[103],
  i2[102],
  i2[101],
  i2[100],
  i2[99],
  i2[98],
  i2[97],
  i2[96],
  i2[95],
  i2[94],
  i2[93],
  i2[92],
  i2[91],
  i2[90],
  i2[89],
  i2[88],
  i2[87],
  i2[86],
  i2[85],
  i2[84],
  i2[83],
  i2[82],
  i2[81],
  i2[80],
  i2[79],
  i2[78],
  i2[77],
  i2[76],
  i2[75],
  i2[74],
  i2[73],
  i2[72],
  i2[71],
  i2[70],
  i2[69],
  i2[68],
  i2[67],
  i2[66],
  i2[65],
  i2[64],
  i2[63],
  i2[62],
  i2[61],
  i2[60],
  i2[59],
  i2[58],
  i2[57],
  i2[56],
  i2[55],
  i2[54],
  i2[53],
  i2[52],
  i2[51],
  i2[50],
  i2[49],
  i2[48],
  i2[47],
  i2[46],
  i2[45],
  i2[44],
  i2[43],
  i2[42],
  i2[41],
  i2[40],
  i2[39],
  i2[38],
  i2[37],
  i2[36],
  i2[35],
  i2[34],
  i2[33],
  i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1]};
assign n9 = n3 ? n7 : n8;
cf_fp_mul_c_11_52_88 s10 (i1, s10_1);
assign o2 = n9;
assign o1 = n6;
endmodule

module cf_fp_mul_c_11_52_30 (i1, i2, o1, o2);
input  [11:0] i1;
input  [102:0] i2;
output [11:0] o1;
output [52:0] o2;
wire   [11:0] s1_1;
wire   [95:0] s1_2;
wire   [11:0] s2_1;
wire   [52:0] s2_2;
wire   [11:0] s3_1;
wire   [96:0] s3_2;
wire   [11:0] s4_1;
wire   [97:0] s4_2;
wire   [11:0] s5_1;
wire   [98:0] s5_2;
wire   [11:0] s6_1;
wire   [99:0] s6_2;
wire   [11:0] s7_1;
wire   [100:0] s7_2;
wire   [11:0] s8_1;
wire   [101:0] s8_2;
cf_fp_mul_c_11_52_86 s1 (s3_1, s3_2, s1_1, s1_2);
cf_fp_mul_c_11_52_37 s2 (s1_1, s1_2, s2_1, s2_2);
cf_fp_mul_c_11_52_36 s3 (s4_1, s4_2, s3_1, s3_2);
cf_fp_mul_c_11_52_35 s4 (s5_1, s5_2, s4_1, s4_2);
cf_fp_mul_c_11_52_34 s5 (s6_1, s6_2, s5_1, s5_2);
cf_fp_mul_c_11_52_33 s6 (s7_1, s7_2, s6_1, s6_2);
cf_fp_mul_c_11_52_32 s7 (s8_1, s8_2, s7_1, s7_2);
cf_fp_mul_c_11_52_31 s8 (i1, i2, s8_1, s8_2);
assign o2 = s2_2;
assign o1 = s2_1;
endmodule

module cf_fp_mul_c_11_52_31 (i1, i2, o1, o2);
input  [11:0] i1;
input  [102:0] i2;
output [11:0] o1;
output [101:0] o2;
wire   n1;
wire   n2;
wire   n3;
wire   [11:0] n4;
wire   [11:0] n5;
wire   [11:0] n6;
wire   [101:0] n7;
wire   [101:0] n8;
wire   [101:0] n9;
wire   s10_1;
assign n1 = i2[102];
assign n2 = n1 | s10_1;
assign n3 = ~n2;
assign n4 = 12'b000000000001;
assign n5 = i1 - n4;
assign n6 = n3 ? n5 : i1;
assign n7 = {i2[101],
  i2[100],
  i2[99],
  i2[98],
  i2[97],
  i2[96],
  i2[95],
  i2[94],
  i2[93],
  i2[92],
  i2[91],
  i2[90],
  i2[89],
  i2[88],
  i2[87],
  i2[86],
  i2[85],
  i2[84],
  i2[83],
  i2[82],
  i2[81],
  i2[80],
  i2[79],
  i2[78],
  i2[77],
  i2[76],
  i2[75],
  i2[74],
  i2[73],
  i2[72],
  i2[71],
  i2[70],
  i2[69],
  i2[68],
  i2[67],
  i2[66],
  i2[65],
  i2[64],
  i2[63],
  i2[62],
  i2[61],
  i2[60],
  i2[59],
  i2[58],
  i2[57],
  i2[56],
  i2[55],
  i2[54],
  i2[53],
  i2[52],
  i2[51],
  i2[50],
  i2[49],
  i2[48],
  i2[47],
  i2[46],
  i2[45],
  i2[44],
  i2[43],
  i2[42],
  i2[41],
  i2[40],
  i2[39],
  i2[38],
  i2[37],
  i2[36],
  i2[35],
  i2[34],
  i2[33],
  i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n8 = {i2[102],
  i2[101],
  i2[100],
  i2[99],
  i2[98],
  i2[97],
  i2[96],
  i2[95],
  i2[94],
  i2[93],
  i2[92],
  i2[91],
  i2[90],
  i2[89],
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