cf_fp_mul_c_11_52.v

verilog浮点乘发器

  i1[24],
  i1[23],
  i1[22],
  i1[21],
  i1[20],
  i1[19],
  i1[18],
  i1[17],
  i1[16],
  i1[15],
  i1[14],
  i1[13],
  i1[12],
  i1[11],
  i1[10],
  i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n2[31];
assign n4 = {n2[30],
  n2[29],
  n2[28],
  n2[27],
  n2[26],
  n2[25],
  n2[24],
  n2[23],
  n2[22],
  n2[21],
  n2[20],
  n2[19],
  n2[18],
  n2[17],
  n2[16],
  n2[15],
  n2[14],
  n2[13],
  n2[12],
  n2[11],
  n2[10],
  n2[9],
  n2[8],
  n2[7],
  n2[6],
  n2[5],
  n2[4],
  n2[3],
  n2[2],
  n2[1],
  n2[0]};
assign n5 = n4[30];
assign n6 = {n4[29],
  n4[28],
  n4[27],
  n4[26],
  n4[25],
  n4[24],
  n4[23],
  n4[22],
  n4[21],
  n4[20],
  n4[19],
  n4[18],
  n4[17],
  n4[16],
  n4[15],
  n4[14],
  n4[13],
  n4[12],
  n4[11],
  n4[10],
  n4[9],
  n4[8],
  n4[7],
  n4[6],
  n4[5],
  n4[4],
  n4[3],
  n4[2],
  n4[1],
  n4[0]};
assign n7 = n6[29];
assign n8 = {n6[28],
  n6[27],
  n6[26],
  n6[25],
  n6[24],
  n6[23],
  n6[22],
  n6[21],
  n6[20],
  n6[19],
  n6[18],
  n6[17],
  n6[16],
  n6[15],
  n6[14],
  n6[13],
  n6[12],
  n6[11],
  n6[10],
  n6[9],
  n6[8],
  n6[7],
  n6[6],
  n6[5],
  n6[4],
  n6[3],
  n6[2],
  n6[1],
  n6[0]};
cf_fp_mul_c_11_52_15 s9 (n8, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12, s9_13, s9_14, s9_15, s9_16, s9_17, s9_18, s9_19, s9_20, s9_21, s9_22, s9_23, s9_24, s9_25, s9_26, s9_27, s9_28, s9_29);
assign o33 = s9_29;
assign o32 = s9_28;
assign o31 = s9_27;
assign o30 = s9_26;
assign o29 = s9_25;
assign o28 = s9_24;
assign o27 = s9_23;
assign o26 = s9_22;
assign o25 = s9_21;
assign o24 = s9_20;
assign o23 = s9_19;
assign o22 = s9_18;
assign o21 = s9_17;
assign o20 = s9_16;
assign o19 = s9_15;
assign o18 = s9_14;
assign o17 = s9_13;
assign o16 = s9_12;
assign o15 = s9_11;
assign o14 = s9_10;
assign o13 = s9_9;
assign o12 = s9_8;
assign o11 = s9_7;
assign o10 = s9_6;
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n7;
assign o3 = n5;
assign o2 = n3;
assign o1 = n1;
endmodule

module cf_fp_mul_c_11_52_15 (i1, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15, o16, o17, o18, o19, o20, o21, o22, o23, o24, o25, o26, o27, o28, o29);
input  [28:0] i1;
output o1;
output o2;
output o3;
output o4;
output o5;
output o6;
output o7;
output o8;
output o9;
output o10;
output o11;
output o12;
output o13;
output o14;
output o15;
output o16;
output o17;
output o18;
output o19;
output o20;
output o21;
output o22;
output o23;
output o24;
output o25;
output o26;
output o27;
output o28;
output o29;
wire   n1;
wire   [27:0] n2;
wire   n3;
wire   [26:0] n4;
wire   n5;
wire   [25:0] n6;
wire   n7;
wire   [24:0] n8;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   s9_6;
wire   s9_7;
wire   s9_8;
wire   s9_9;
wire   s9_10;
wire   s9_11;
wire   s9_12;
wire   s9_13;
wire   s9_14;
wire   s9_15;
wire   s9_16;
wire   s9_17;
wire   s9_18;
wire   s9_19;
wire   s9_20;
wire   s9_21;
wire   s9_22;
wire   s9_23;
wire   s9_24;
wire   s9_25;
assign n1 = i1[28];
assign n2 = {i1[27],
  i1[26],
  i1[25],
  i1[24],
  i1[23],
  i1[22],
  i1[21],
  i1[20],
  i1[19],
  i1[18],
  i1[17],
  i1[16],
  i1[15],
  i1[14],
  i1[13],
  i1[12],
  i1[11],
  i1[10],
  i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n2[27];
assign n4 = {n2[26],
  n2[25],
  n2[24],
  n2[23],
  n2[22],
  n2[21],
  n2[20],
  n2[19],
  n2[18],
  n2[17],
  n2[16],
  n2[15],
  n2[14],
  n2[13],
  n2[12],
  n2[11],
  n2[10],
  n2[9],
  n2[8],
  n2[7],
  n2[6],
  n2[5],
  n2[4],
  n2[3],
  n2[2],
  n2[1],
  n2[0]};
assign n5 = n4[26];
assign n6 = {n4[25],
  n4[24],
  n4[23],
  n4[22],
  n4[21],
  n4[20],
  n4[19],
  n4[18],
  n4[17],
  n4[16],
  n4[15],
  n4[14],
  n4[13],
  n4[12],
  n4[11],
  n4[10],
  n4[9],
  n4[8],
  n4[7],
  n4[6],
  n4[5],
  n4[4],
  n4[3],
  n4[2],
  n4[1],
  n4[0]};
assign n7 = n6[25];
assign n8 = {n6[24],
  n6[23],
  n6[22],
  n6[21],
  n6[20],
  n6[19],
  n6[18],
  n6[17],
  n6[16],
  n6[15],
  n6[14],
  n6[13],
  n6[12],
  n6[11],
  n6[10],
  n6[9],
  n6[8],
  n6[7],
  n6[6],
  n6[5],
  n6[4],
  n6[3],
  n6[2],
  n6[1],
  n6[0]};
cf_fp_mul_c_11_52_16 s9 (n8, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12, s9_13, s9_14, s9_15, s9_16, s9_17, s9_18, s9_19, s9_20, s9_21, s9_22, s9_23, s9_24, s9_25);
assign o29 = s9_25;
assign o28 = s9_24;
assign o27 = s9_23;
assign o26 = s9_22;
assign o25 = s9_21;
assign o24 = s9_20;
assign o23 = s9_19;
assign o22 = s9_18;
assign o21 = s9_17;
assign o20 = s9_16;
assign o19 = s9_15;
assign o18 = s9_14;
assign o17 = s9_13;
assign o16 = s9_12;
assign o15 = s9_11;
assign o14 = s9_10;
assign o13 = s9_9;
assign o12 = s9_8;
assign o11 = s9_7;
assign o10 = s9_6;
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n7;
assign o3 = n5;
assign o2 = n3;
assign o1 = n1;
endmodule

module cf_fp_mul_c_11_52_16 (i1, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15, o16, o17, o18, o19, o20, o21, o22, o23, o24, o25);
input  [24:0] i1;
output o1;
output o2;
output o3;
output o4;
output o5;
output o6;
output o7;
output o8;
output o9;
output o10;
output o11;
output o12;
output o13;
output o14;
output o15;
output o16;
output o17;
output o18;
output o19;
output o20;
output o21;
output o22;
output o23;
output o24;
output o25;
wire   n1;
wire   [23:0] n2;
wire   n3;
wire   [22:0] n4;
wire   n5;
wire   [21:0] n6;
wire   n7;
wire   [20:0] n8;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   s9_6;
wire   s9_7;
wire   s9_8;
wire   s9_9;
wire   s9_10;
wire   s9_11;
wire   s9_12;
wire   s9_13;
wire   s9_14;
wire   s9_15;
wire   s9_16;
wire   s9_17;
wire   s9_18;
wire   s9_19;
wire   s9_20;
wire   s9_21;
assign n1 = i1[24];
assign n2 = {i1[23],
  i1[22],
  i1[21],
  i1[20],
  i1[19],
  i1[18],
  i1[17],
  i1[16],
  i1[15],
  i1[14],
  i1[13],
  i1[12],
  i1[11],
  i1[10],
  i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n2[23];
assign n4 = {n2[22],
  n2[21],
  n2[20],
  n2[19],
  n2[18],
  n2[17],
  n2[16],
  n2[15],
  n2[14],
  n2[13],
  n2[12],
  n2[11],
  n2[10],
  n2[9],
  n2[8],
  n2[7],
  n2[6],
  n2[5],
  n2[4],
  n2[3],
  n2[2],
  n2[1],
  n2[0]};
assign n5 = n4[22];
assign n6 = {n4[21],
  n4[20],
  n4[19],
  n4[18],
  n4[17],
  n4[16],
  n4[15],
  n4[14],
  n4[13],
  n4[12],
  n4[11],
  n4[10],
  n4[9],
  n4[8],
  n4[7],
  n4[6],
  n4[5],
  n4[4],
  n4[3],
  n4[2],
  n4[1],
  n4[0]};
assign n7 = n6[21];
assign n8 = {n6[20],
  n6[19],
  n6[18],
  n6[17],
  n6[16],
  n6[15],
  n6[14],
  n6[13],
  n6[12],
  n6[11],
  n6[10],
  n6[9],
  n6[8],
  n6[7],
  n6[6],
  n6[5],
  n6[4],
  n6[3],
  n6[2],
  n6[1],
  n6[0]};
cf_fp_mul_c_11_52_17 s9 (n8, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12, s9_13, s9_14, s9_15, s9_16, s9_17, s9_18, s9_19, s9_20, s9_21);
assign o25 = s9_21;
assign o24 = s9_20;
assign o23 = s9_19;
assign o22 = s9_18;
assign o21 = s9_17;
assign o20 = s9_16;
assign o19 = s9_15;
assign o18 = s9_14;
assign o17 = s9_13;
assign o16 = s9_12;
assign o15 = s9_11;
assign o14 = s9_10;
assign o13 = s9_9;
assign o12 = s9_8;
assign o11 = s9_7;
assign o10 = s9_6;
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n7;
assign o3 = n5;
assign o2 = n3;
assign o1 = n1;
endmodule

module cf_fp_mul_c_11_52_17 (i1, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15, o16, o17, o18, o19, o20, o21);
input  [20:0] i1;
output o1;
output o2;
output o3;
output o4;
output o5;
output o6;
output o7;
output o8;
output o9;
output o10;
output o11;
output o12;
output o13;
output o14;
output o15;
output o16;
output o17;
output o18;
output o19;
output o20;
output o21;
wire   n1;
wire   [19:0] n2;
wire   n3;
wire   [18:0] n4;
wire   n5;
wire   [17:0] n6;
wire   n7;
wire   [16:0] n8;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   s9_6;
wire   s9_7;
wire   s9_8;
wire   s9_9;
wire   s9_10;
wire   s9_11;
wire   s9_12;
wire   s9_13;
wire   s9_14;
wire   s9_15;
wire   s9_16;
wire   s9_17;
assign n1 = i1[20];
assign n2 = {i1[19],
  i1[18],
  i1[17],
  i1[16],
  i1[15],
  i1[14],
  i1[13],
  i1[12],
  i1[11],
  i1[10],
  i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n2[19];
assign n4 = {n2[18],
  n2[17],
  n2[16],
  n2[15],
  n2[14],
  n2[13],
  n2[12],
  n2[11],
  n2[10],
  n2[9],
  n2[8],
  n2[7],
  n2[6],
  n2[5],
  n2[4],
  n2[3],
  n2[2],
  n2[1],
  n2[0]};
assign n5 = n4[18];
assign n6 = {n4[17],
  n4[16],
  n4[15],
  n4[14],
  n4[13],
  n4[12],
  n4[11],
  n4[10],
  n4[9],
  n4[8],
  n4[7],
  n4[6],
  n4[5],
  n4[4],
  n4[3],
  n4[2],
  n4[1],
  n4[0]};
assign n7 = n6[17];
assign n8 = {n6[16],
  n6[15],
  n6[14],
  n6[13],
  n6[12],
  n6[11],
  n6[10],
  n6[9],
  n6[8],
  n6[7],
  n6[6],
  n6[5],
  n6[4],
  n6[3],
  n6[2],
  n6[1],
  n6[0]};
cf_fp_mul_c_11_52_18 s9 (n8, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12, s9_13, s9_14, s9_15, s9_16, s9_17);
assign o21 = s9_17;
assign o20 = s9_16;
assign o19 = s9_15;
assign o18 = s9_14;
assign o17 = s9_13;
assign o16 = s9_12;
assign o15 = s9_11;
assign o14 = s9_10;
assign o13 = s9_9;
assign o12 = s9_8;
assign o11 = s9_7;
assign o10 = s9_6;
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n7;
assign o3 = n5;
assign o2 = n3;
assign o1 = n1;
endmodule

module cf_fp_mul_c_11_52_18 (i1, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15, o16, o17);
input  [16:0] i1;
output o1;
output o2;
output o3;
output o4;
output o5;
output o6;
output o7;
output o8;
output o9;
output o10;
output o11;
output o12;
output o13;
output o14;
output o15;
output o16;
output o17;
wire   n1;
wire   [15:0] n2;
wire   n3;
wire   [14:0] n4;
wire   n5;
wire   [13:0] n6;
wire   n7;
wire   [12:0] n8;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   s9_6;
wire   s9_7;
wire   s9_8;
wire   s9_9;
wire   s9_10;
wire   s9_11;
wire   s9_12;
wire   s9_13;
assign n1 = i1[16];
assign n2 = {i1[15],
  i1[14],
  i1[13],
  i1[12],
  i1[11],
  i1[10],
  i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n2[15];
assign n4 = {n2[14],
  n2[13],
  n2[12],
  n2[11],
  n2[10],
  n2[9],
  n2[8],
  n2[7],
  n2[6],
  n2[5],
  n2[4],
  n2[3],
  n2[2],
  n2[1],
  n2[0]};
assign n5 = n4[14];
assign n6 = {n4[13],
  n4[12],
  n4[11],
  n4[10],
  n4[9],
  n4[8],
  n4[7],
  n4[6],
  n4[5],
  n4[4],
  n4[3],
  n4[2],
  n4[1],
  n4[0]};
assign n7 = n6[13];
assign n8 = {n6[12],
  n6[11],
  n6[10],
  n6[9],
  n6[8],
  n6[7],
  n6[6],
  n6[5],
  n6[4],
  n6[3],
  n6[2],
  n6[1],
  n6[0]};
cf_fp_mul_c_11_52_19 s9 (n8, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12, s9_13);
assign o17 = s9_13;
assign o16 = s9_12;
assign o15 = s9_11;
assign o14 = s9_10;
assign o13 = s9_9;
assign o12 = s9_8;
assign o11 = s9_7;
assign o10 = s9_6;
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n7;
assign o3 = n5;
assign o2 = n3;
assign o1 = n1;
endmodule

module cf_fp_mul_c_11_52_19 (i1, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13);
input  [12:0] i1;
output o1;
output o2;
output o3;
output o4;
output o5;
output o6;
output o7;
output o8;
output o9;
output o10;
output o11;
output o12;
output o13;
wire   n1;
wire   [11:0] n2;
wire   n3;
wire   [10:0] n4;
wire   n5;
wire   [9:0] n6;
wire   n7;
wire   [8:0] n8;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   s9_6;
wire   s9_7;
wire   s9_8;
wire   s9_9;
assign n1 = i1[12];
assign n2 = {i1[11],
  i1[10],
  i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n2[11];
assign n4 = {n2[10],
  n2[9],
  n2[8],
  n2[7],
  n2[6],
  n2[5],
  n2[4],
  n2[3],
  n2[2],
  n2[1],
  n2[0]};
assign n5 = n4[10];
assign n6 = {n4[9],
  n4[8],
  n4[7],
  n4[6],
  n4[5],
  n4[4],
  n4[3],