cf_fp_mul_c_11_52.v

verilog浮点乘发器

  n4[38],
  n4[37],
  n4[36],
  n4[35],
  n4[34],
  n4[33],
  n4[32],
  n4[31],
  n4[30],
  n4[29],
  n4[28],
  n4[27],
  n4[26],
  n4[25],
  n4[24],
  n4[23],
  n4[22],
  n4[21],
  n4[20],
  n4[19],
  n4[18],
  n4[17],
  n4[16],
  n4[15],
  n4[14],
  n4[13],
  n4[12],
  n4[11],
  n4[10],
  n4[9],
  n4[8],
  n4[7],
  n4[6],
  n4[5],
  n4[4],
  n4[3],
  n4[2],
  n4[1],
  n4[0]};
assign n7 = ~s9_1;
cf_fp_mul_c_11_52_10 s8 (n6, s8_1, s8_2, s8_3, s8_4, s8_5, s8_6, s8_7, s8_8, s8_9, s8_10, s8_11, s8_12, s8_13, s8_14, s8_15, s8_16, s8_17, s8_18, s8_19, s8_20, s8_21, s8_22, s8_23, s8_24, s8_25, s8_26, s8_27, s8_28, s8_29, s8_30, s8_31, s8_32, s8_33, s8_34, s8_35, s8_36, s8_37, s8_38, s8_39, s8_40, s8_41, s8_42, s8_43, s8_44, s8_45, s8_46, s8_47, s8_48, s8_49);
cf_fp_mul_c_11_52_5 s9 (n1, n3, n5, s8_1, s8_2, s8_3, s8_4, s8_5, s8_6, s8_7, s8_8, s8_9, s8_10, s8_11, s8_12, s8_13, s8_14, s8_15, s8_16, s8_17, s8_18, s8_19, s8_20, s8_21, s8_22, s8_23, s8_24, s8_25, s8_26, s8_27, s8_28, s8_29, s8_30, s8_31, s8_32, s8_33, s8_34, s8_35, s8_36, s8_37, s8_38, s8_39, s8_40, s8_41, s8_42, s8_43, s8_44, s8_45, s8_46, s8_47, s8_48, s8_49, s9_1);
assign o1 = n7;
endmodule

module cf_fp_mul_c_11_52_5 (i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50, i51, i52, o1);
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  i8;
input  i9;
input  i10;
input  i11;
input  i12;
input  i13;
input  i14;
input  i15;
input  i16;
input  i17;
input  i18;
input  i19;
input  i20;
input  i21;
input  i22;
input  i23;
input  i24;
input  i25;
input  i26;
input  i27;
input  i28;
input  i29;
input  i30;
input  i31;
input  i32;
input  i33;
input  i34;
input  i35;
input  i36;
input  i37;
input  i38;
input  i39;
input  i40;
input  i41;
input  i42;
input  i43;
input  i44;
input  i45;
input  i46;
input  i47;
input  i48;
input  i49;
input  i50;
input  i51;
input  i52;
output o1;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   n5;
wire   n6;
wire   n7;
wire   n8;
wire   n9;
wire   s10_1;
wire   s10_2;
wire   s10_3;
wire   s10_4;
wire   s10_5;
wire   s10_6;
wire   s10_7;
wire   s10_8;
wire   s10_9;
wire   s10_10;
wire   s10_11;
wire   s10_12;
wire   s10_13;
wire   s10_14;
wire   s10_15;
wire   s10_16;
wire   s10_17;
wire   s10_18;
wire   s10_19;
wire   s10_20;
wire   s10_21;
wire   s10_22;
wire   s11_1;
wire   s11_2;
wire   s11_3;
wire   s11_4;
wire   s11_5;
wire   s11_6;
wire   s11_7;
wire   s11_8;
wire   s12_1;
assign n1 = i1 | i2;
assign n2 = i3 | i4;
assign n3 = i5 | i6;
assign n4 = i7 | i8;
assign n5 = n1 | n2;
assign n6 = n3 | n4;
assign n7 = s10_1 | s10_2;
assign n8 = s10_3 | s10_4;
assign n9 = s10_5 | s10_6;
cf_fp_mul_c_11_52_7 s10 (i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50, i51, i52, s10_1, s10_2, s10_3, s10_4, s10_5, s10_6, s10_7, s10_8, s10_9, s10_10, s10_11, s10_12, s10_13, s10_14, s10_15, s10_16, s10_17, s10_18, s10_19, s10_20, s10_21, s10_22);
cf_fp_mul_c_11_52_9 s11 (s10_7, s10_8, s10_9, s10_10, s10_11, s10_12, s10_13, s10_14, s10_15, s10_16, s10_17, s10_18, s10_19, s10_20, s10_21, s10_22, s11_1, s11_2, s11_3, s11_4, s11_5, s11_6, s11_7, s11_8);
cf_fp_mul_c_11_52_6 s12 (n5, n6, n7, n8, n9, s11_1, s11_2, s11_3, s11_4, s11_5, s11_6, s11_7, s11_8, s12_1);
assign o1 = s12_1;
endmodule

module cf_fp_mul_c_11_52_6 (i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, o1);
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  i8;
input  i9;
input  i10;
input  i11;
input  i12;
input  i13;
output o1;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   n5;
wire   n6;
wire   n7;
wire   n8;
wire   n9;
wire   n10;
wire   n11;
wire   n12;
assign n1 = i1 | i2;
assign n2 = i3 | i4;
assign n3 = i5 | i6;
assign n4 = i7 | i8;
assign n5 = i9 | i10;
assign n6 = i11 | i12;
assign n7 = n1 | n2;
assign n8 = n3 | n4;
assign n9 = n5 | n6;
assign n10 = n7 | n8;
assign n11 = n9 | i13;
assign n12 = n10 | n11;
assign o1 = n12;
endmodule

module cf_fp_mul_c_11_52_7 (i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15, o16, o17, o18, o19, o20, o21, o22);
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  i8;
input  i9;
input  i10;
input  i11;
input  i12;
input  i13;
input  i14;
input  i15;
input  i16;
input  i17;
input  i18;
input  i19;
input  i20;
input  i21;
input  i22;
input  i23;
input  i24;
input  i25;
input  i26;
input  i27;
input  i28;
input  i29;
input  i30;
input  i31;
input  i32;
input  i33;
input  i34;
input  i35;
input  i36;
input  i37;
input  i38;
input  i39;
input  i40;
input  i41;
input  i42;
input  i43;
input  i44;
output o1;
output o2;
output o3;
output o4;
output o5;
output o6;
output o7;
output o8;
output o9;
output o10;
output o11;
output o12;
output o13;
output o14;
output o15;
output o16;
output o17;
output o18;
output o19;
output o20;
output o21;
output o22;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   n5;
wire   n6;
wire   n7;
wire   s8_1;
wire   s8_2;
wire   s8_3;
wire   s8_4;
wire   s8_5;
wire   s8_6;
wire   s8_7;
wire   s8_8;
wire   s8_9;
wire   s8_10;
wire   s8_11;
wire   s8_12;
wire   s8_13;
wire   s8_14;
wire   s8_15;
assign n1 = i1 | i2;
assign n2 = i3 | i4;
assign n3 = i5 | i6;
assign n4 = i7 | i8;
assign n5 = i9 | i10;
assign n6 = i11 | i12;
assign n7 = i13 | i14;
cf_fp_mul_c_11_52_8 s8 (i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, s8_1, s8_2, s8_3, s8_4, s8_5, s8_6, s8_7, s8_8, s8_9, s8_10, s8_11, s8_12, s8_13, s8_14, s8_15);
assign o22 = s8_15;
assign o21 = s8_14;
assign o20 = s8_13;
assign o19 = s8_12;
assign o18 = s8_11;
assign o17 = s8_10;
assign o16 = s8_9;
assign o15 = s8_8;
assign o14 = s8_7;
assign o13 = s8_6;
assign o12 = s8_5;
assign o11 = s8_4;
assign o10 = s8_3;
assign o9 = s8_2;
assign o8 = s8_1;
assign o7 = n7;
assign o6 = n6;
assign o5 = n5;
assign o4 = n4;
assign o3 = n3;
assign o2 = n2;
assign o1 = n1;
endmodule

module cf_fp_mul_c_11_52_8 (i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15);
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  i8;
input  i9;
input  i10;
input  i11;
input  i12;
input  i13;
input  i14;
input  i15;
input  i16;
input  i17;
input  i18;
input  i19;
input  i20;
input  i21;
input  i22;
input  i23;
input  i24;
input  i25;
input  i26;
input  i27;
input  i28;
input  i29;
input  i30;
output o1;
output o2;
output o3;
output o4;
output o5;
output o6;
output o7;
output o8;
output o9;
output o10;
output o11;
output o12;
output o13;
output o14;
output o15;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   n5;
wire   n6;
wire   n7;
wire   s8_1;
wire   s8_2;
wire   s8_3;
wire   s8_4;
wire   s8_5;
wire   s8_6;
wire   s8_7;
wire   s8_8;
assign n1 = i1 | i2;
assign n2 = i3 | i4;
assign n3 = i5 | i6;
assign n4 = i7 | i8;
assign n5 = i9 | i10;
assign n6 = i11 | i12;
assign n7 = i13 | i14;
cf_fp_mul_c_11_52_9 s8 (i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, s8_1, s8_2, s8_3, s8_4, s8_5, s8_6, s8_7, s8_8);
assign o15 = s8_8;
assign o14 = s8_7;
assign o13 = s8_6;
assign o12 = s8_5;
assign o11 = s8_4;
assign o10 = s8_3;
assign o9 = s8_2;
assign o8 = s8_1;
assign o7 = n7;
assign o6 = n6;
assign o5 = n5;
assign o4 = n4;
assign o3 = n3;
assign o2 = n2;
assign o1 = n1;
endmodule

module cf_fp_mul_c_11_52_9 (i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, o1, o2, o3, o4, o5, o6, o7, o8);
input  i1;
input  i2;
input  i3;
input  i4;
input  i5;
input  i6;
input  i7;
input  i8;
input  i9;
input  i10;
input  i11;
input  i12;
input  i13;
input  i14;
input  i15;
input  i16;
output o1;
output o2;
output o3;
output o4;
output o5;
output o6;
output o7;
output o8;
wire   n1;
wire   n2;
wire   n3;
wire   n4;
wire   n5;
wire   n6;
wire   n7;
wire   n8;
assign n1 = i1 | i2;
assign n2 = i3 | i4;
assign n3 = i5 | i6;
assign n4 = i7 | i8;
assign n5 = i9 | i10;
assign n6 = i11 | i12;
assign n7 = i13 | i14;
assign n8 = i15 | i16;
assign o8 = n8;
assign o7 = n7;
assign o6 = n6;
assign o5 = n5;
assign o4 = n4;
assign o3 = n3;
assign o2 = n2;
assign o1 = n1;
endmodule

module cf_fp_mul_c_11_52_10 (i1, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15, o16, o17, o18, o19, o20, o21, o22, o23, o24, o25, o26, o27, o28, o29, o30, o31, o32, o33, o34, o35, o36, o37, o38, o39, o40, o41, o42, o43, o44, o45, o46, o47, o48, o49);
input  [48:0] i1;
output o1;
output o2;
output o3;
output o4;
output o5;
output o6;
output o7;
output o8;
output o9;
output o10;
output o11;
output o12;
output o13;
output o14;
output o15;
output o16;
output o17;
output o18;
output o19;
output o20;
output o21;
output o22;
output o23;
output o24;
output o25;
output o26;
output o27;
output o28;
output o29;
output o30;
output o31;
output o32;
output o33;
output o34;
output o35;
output o36;
output o37;
output o38;
output o39;
output o40;
output o41;
output o42;
output o43;
output o44;
output o45;
output o46;
output o47;
output o48;
output o49;
wire   n1;
wire   [47:0] n2;
wire   n3;
wire   [46:0] n4;
wire   n5;
wire   [45:0] n6;
wire   n7;
wire   [44:0] n8;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   s9_6;
wire   s9_7;
wire   s9_8;
wire   s9_9;
wire   s9_10;
wire   s9_11;
wire   s9_12;
wire   s9_13;
wire   s9_14;
wire   s9_15;
wire   s9_16;
wire   s9_17;
wire   s9_18;
wire   s9_19;
wire   s9_20;
wire   s9_21;
wire   s9_22;
wire   s9_23;
wire   s9_24;
wire   s9_25;
wire   s9_26;
wire   s9_27;
wire   s9_28;
wire   s9_29;
wire   s9_30;
wire   s9_31;
wire   s9_32;
wire   s9_33;
wire   s9_34;
wire   s9_35;
wire   s9_36;
wire   s9_37;
wire   s9_38;
wire   s9_39;
wire   s9_40;
wire   s9_41;
wire   s9_42;
wire   s9_43;
wire   s9_44;
wire   s9_45;
assign n1 = i1[48];
assign n2 = {i1[47],
  i1[46],
  i1[45],
  i1[44],
  i1[43],
  i1[42],
  i1[41],
  i1[40],
  i1[39],
  i1[38],
  i1[37],
  i1[36],
  i1[35],
  i1[34],
  i1[33],
  i1[32],
  i1[31],
  i1[30],
  i1[29],
  i1[28],
  i1[27],
  i1[26],
  i1[25],
  i1[24],
  i1[23],
  i1[22],
  i1[21],
  i1[20],
  i1[19],
  i1[18],
  i1[17],
  i1[16],
  i1[15],
  i1[14],
  i1[13],
  i1[12],
  i1[11],
  i1[10],
  i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n2[47];
assign n4 = {n2[46],
  n2[45],
  n2[44],
  n2[43],
  n2[42],
  n2[41],
  n2[40],
  n2[39],
  n2[38],
  n2[37],
  n2[36],
  n2[35],
  n2[34],
  n2[33],
  n2[32],
  n2[31],
  n2[30],
  n2[29],
  n2[28],
  n2[27],
  n2[26],
  n2[25],
  n2[24],
  n2[23],
  n2[22],
  n2[21],
  n2[20],
  n2[19],
  n2[18],
  n2[17],
  n2[16],
  n2[15],
  n2[14],
  n2[13],
  n2[12],
  n2[11],
  n2[10],
  n2[9],
  n2[8],
  n2[7],
  n2[6],
  n2[5],
  n2[4],
  n2[3],
  n2[2],
  n2[1],
  n2[0]};
assign n5 = n4[46];
assign n6 = {n4[45],
  n4[44],
  n4[43],
  n4[42],
  n4[41],
  n4[40],
  n4[39],
  n4[38],
  n4[37],
  n4[36],
  n4[35],
  n4[34],
  n4[33],
  n4[32],
  n4[31],
  n4[30],
  n4[29],
  n4[28],
  n4[27],
  n4[26],
  n4[25],
  n4[24],
  n4[23],
  n4[22],
  n4[21],
  n4[20],
  n4[19],
  n4[18],
  n4[17],
  n4[16],
  n4[15],
  n4[14],
  n4[13],
  n4[12],
  n4[11],
  n4[10],
  n4[9],
  n4[8],
  n4[7],
  n4[6],
  n4[5],
  n4[4],
  n4[3],
  n4[2],
  n4[1],
  n4[0]};
assign n7 = n6[45];
assign n8 = {n6[44],
  n6[43],
  n6[42],
  n6[41],
  n6[40],
  n6[39],
  n6[38],
  n6[37],
  n6[36],
  n6[35],
  n6[34],
  n6[33],
  n6[32],
  n6[31],
  n6[30],
  n6[29],
  n6[28],
  n6[27],
  n6[26],
  n6[25],
  n6[24],
  n6[23],
  n6[22],
  n6[21],
  n6[20],
  n6[19],
  n6[18],
  n6[17],
  n6[16],
  n6[15],
  n6[14],
  n6[13],
  n6[12],
  n6[11],
  n6[10],
  n6[9],
  n6[8],
  n6[7],
  n6[6],
  n6[5],
  n6[4],
  n6[3],
  n6[2],
  n6[1],
  n6[0]};
cf_fp_mul_c_11_52_11 s9 (n8, s9_1, s9_2, s9_3, s9_4, s9_5, s9_6, s9_7, s9_8, s9_9, s9_10, s9_11, s9_12, s9_13, s9_14, s9_15, s9_16, s9_17, s9_18, s9_19, s9_20, s9_21, s9_22, s9_23, s9_24, s9_25, s9_26, s9_27, s9_28, s9_29, s9_30, s9_31, s9_32, s9_33, s9_34, s9_35, s9_36, s9_37, s9_38, s9_39, s9_40, s9_41, s9_42, s9_43, s9_44, s9_45);
assign o49 = s9_45;
assign o48 = s9_44;
assign o47 = s9_43;
assign o46 = s9_42;
assign o45 = s9_41;
assign o44 = s9_40;
assign o43 = s9_39;
assign o42 = s9_38;
assign o41 = s9_37;
assign o40 = s9_36;
assign o39 = s9_35;
assign o38 = s9_34;
assign o37 = s9_33;
assign o36 = s9_32;
assign o35 = s9_31;
assign o34 = s9_30;
assign o33 = s9_29;
assign o32 = s9_28;
assign o31 = s9_27;
assign o30 = s9_26;
assign o29 = s9_25;
assign o28 = s9_24;
assign o27 = s9_23;
assign o26 = s9_22;
assign o25 = s9_21;
assign o24 = s9_20;
assign o23 = s9_19;
assign o22 = s9_18;
assign o21 = s9_17;
assign o20 = s9_16;
assign o19 = s9_15;
assign o18 = s9_14;
assign o17 = s9_13;
assign o16 = s9_12;
assign o15 = s9_11;
assign o14 = s9_10;
assign o13 = s9_9;
assign o12 = s9_8;
assign o11 = s9_7;
assign o10 = s9_6;
assign o9 = s9_5;
assign o8 = s9_4;
assign o7 = s9_3;
assign o6 = s9_2;
assign o5 = s9_1;
assign o4 = n7;
assign o3 = n5;
assign o2 = n3;
assign o1 = n1;
endmodule

module cf_fp_mul_c_11_52_11 (i1, o1, o2, o3, o4, o5, o6, o7, o8, o9, o10, o11, o12, o13, o14, o15, o16, o17, o18, o19, o20, o21, o22, o23, o24, o25, o26, o27, o28, o29, o30, o31, o32, o33, o34, o35, o36, o37, o38, o39, o40, o41, o42, o43, o44, o45);
input  [44:0] i1;
output o1;
output o2;
output o3;
output o4;
output o5;
output o6;
output o7;
output o8;
output o9;
output o10;
output o11;
output o12;
output o13;
output o14;
output o15;
output o16;
output o17;
output o18;
output o19;
output o20;
output o21;
output o22;
output o23;
output o24;
output o25;
output o26;
output o27;
output o28;
output o29;
output o30;
output o31;
output o32;
output o33;
output o34;
output o35;
output o36;
output o37;
output o38;
output o39;
output o40;
output o41;
output o42;
output o43;
output o44;
output o45;
wire   n1;
wire   [43:0] n2;
wire   n3;
wire   [42:0] n4;
wire   n5;
wire   [41:0] n6;
wire   n7;
wire   [40:0] n8;
wire   s9_1;
wire   s9_2;
wire   s9_3;
wire   s9_4;
wire   s9_5;
wire   s9_6;
wire   s9_7;
wire   s9_8;
wire   s9_9;
wire   s9_10;
wire   s9_11;
wire   s9_12;
wire   s9_13;
wire   s9_14;
wire   s9_15;
wire   s9_16;
wire   s9_17;
wire   s9_18;
wire   s9_19;
wire   s9_20;