cf_fp_mul_c_11_52.v

verilog浮点乘发器

//
//  Copyright (c) 2003 Launchbird Design Systems, Inc.
//  All rights reserved.
//  
//  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
//    Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
//    Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
//  
//  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
//  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
//  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//  
//  
//  Overview:
//  
//    Performs floating point multiply.
//  
//  Interface:
//  
//  
//  
//    Inputs:
//      a_i : Left operand.
//      b_i : Right operand.
//  
//    Outputs:
//      x_o : Result.
//  
//  Built In Parameters:
//  
//    Exponent Precision = 11
//    Mantissa Precision = 52
//    Total    Precision = 64
//  
//  
//  
//  
//  
//  Generated by Confluence 0.6.3  --  Launchbird Design Systems, Inc.  --  www.launchbird.com
//  
//  Build Date : Fri Aug 22 09:47:15 CDT 2003
//  
//  Interface
//  
//    Build Name    : cf_fp_mul_c_11_52
//    Clock Domains : 
//    Vector Input  : a_i(64)
//    Vector Input  : b_i(64)
//    Vector Output : x_o(64)
//  
//  
//  

`timescale 1 ns / 1 ns

module cf_fp_mul_c_11_52 (a_i, b_i, x_o);
input  [63:0] a_i;
input  [63:0] b_i;
output [63:0] x_o;
wire   [63:0] n1;
cf_fp_mul_c_11_52_1 s1 (a_i, b_i, n1);
assign x_o = n1;
endmodule

module cf_fp_mul_c_11_52_1 (i1, i2, o1);
input  [63:0] i1;
input  [63:0] i2;
output [63:0] o1;
wire   n1;
wire   [11:0] n2;
wire   [11:0] n3;
wire   [11:0] n4;
wire   [104:0] n5;
wire   [104:0] n6;
wire   [104:0] n7;
wire   [11:0] s8_1;
wire   [102:0] s8_2;
wire   [11:0] s9_1;
wire   [52:0] s9_2;
wire   [11:0] s10_1;
wire   [103:0] s10_2;
wire   [63:0] s11_1;
wire   s12_1;
wire   s12_2;
wire   s12_3;
wire   s12_4;
wire   s12_5;
wire   [11:0] s12_6;
wire   [105:0] s12_7;
assign n1 = s12_7[105];
assign n2 = 12'b000000000001;
assign n3 = s12_6 + n2;
assign n4 = n1 ? n3 : s12_6;
assign n5 = {s12_7[105],
  s12_7[104],
  s12_7[103],
  s12_7[102],
  s12_7[101],
  s12_7[100],
  s12_7[99],
  s12_7[98],
  s12_7[97],
  s12_7[96],
  s12_7[95],
  s12_7[94],
  s12_7[93],
  s12_7[92],
  s12_7[91],
  s12_7[90],
  s12_7[89],
  s12_7[88],
  s12_7[87],
  s12_7[86],
  s12_7[85],
  s12_7[84],
  s12_7[83],
  s12_7[82],
  s12_7[81],
  s12_7[80],
  s12_7[79],
  s12_7[78],
  s12_7[77],
  s12_7[76],
  s12_7[75],
  s12_7[74],
  s12_7[73],
  s12_7[72],
  s12_7[71],
  s12_7[70],
  s12_7[69],
  s12_7[68],
  s12_7[67],
  s12_7[66],
  s12_7[65],
  s12_7[64],
  s12_7[63],
  s12_7[62],
  s12_7[61],
  s12_7[60],
  s12_7[59],
  s12_7[58],
  s12_7[57],
  s12_7[56],
  s12_7[55],
  s12_7[54],
  s12_7[53],
  s12_7[52],
  s12_7[51],
  s12_7[50],
  s12_7[49],
  s12_7[48],
  s12_7[47],
  s12_7[46],
  s12_7[45],
  s12_7[44],
  s12_7[43],
  s12_7[42],
  s12_7[41],
  s12_7[40],
  s12_7[39],
  s12_7[38],
  s12_7[37],
  s12_7[36],
  s12_7[35],
  s12_7[34],
  s12_7[33],
  s12_7[32],
  s12_7[31],
  s12_7[30],
  s12_7[29],
  s12_7[28],
  s12_7[27],
  s12_7[26],
  s12_7[25],
  s12_7[24],
  s12_7[23],
  s12_7[22],
  s12_7[21],
  s12_7[20],
  s12_7[19],
  s12_7[18],
  s12_7[17],
  s12_7[16],
  s12_7[15],
  s12_7[14],
  s12_7[13],
  s12_7[12],
  s12_7[11],
  s12_7[10],
  s12_7[9],
  s12_7[8],
  s12_7[7],
  s12_7[6],
  s12_7[5],
  s12_7[4],
  s12_7[3],
  s12_7[2],
  s12_7[1]};
assign n6 = {s12_7[104],
  s12_7[103],
  s12_7[102],
  s12_7[101],
  s12_7[100],
  s12_7[99],
  s12_7[98],
  s12_7[97],
  s12_7[96],
  s12_7[95],
  s12_7[94],
  s12_7[93],
  s12_7[92],
  s12_7[91],
  s12_7[90],
  s12_7[89],
  s12_7[88],
  s12_7[87],
  s12_7[86],
  s12_7[85],
  s12_7[84],
  s12_7[83],
  s12_7[82],
  s12_7[81],
  s12_7[80],
  s12_7[79],
  s12_7[78],
  s12_7[77],
  s12_7[76],
  s12_7[75],
  s12_7[74],
  s12_7[73],
  s12_7[72],
  s12_7[71],
  s12_7[70],
  s12_7[69],
  s12_7[68],
  s12_7[67],
  s12_7[66],
  s12_7[65],
  s12_7[64],
  s12_7[63],
  s12_7[62],
  s12_7[61],
  s12_7[60],
  s12_7[59],
  s12_7[58],
  s12_7[57],
  s12_7[56],
  s12_7[55],
  s12_7[54],
  s12_7[53],
  s12_7[52],
  s12_7[51],
  s12_7[50],
  s12_7[49],
  s12_7[48],
  s12_7[47],
  s12_7[46],
  s12_7[45],
  s12_7[44],
  s12_7[43],
  s12_7[42],
  s12_7[41],
  s12_7[40],
  s12_7[39],
  s12_7[38],
  s12_7[37],
  s12_7[36],
  s12_7[35],
  s12_7[34],
  s12_7[33],
  s12_7[32],
  s12_7[31],
  s12_7[30],
  s12_7[29],
  s12_7[28],
  s12_7[27],
  s12_7[26],
  s12_7[25],
  s12_7[24],
  s12_7[23],
  s12_7[22],
  s12_7[21],
  s12_7[20],
  s12_7[19],
  s12_7[18],
  s12_7[17],
  s12_7[16],
  s12_7[15],
  s12_7[14],
  s12_7[13],
  s12_7[12],
  s12_7[11],
  s12_7[10],
  s12_7[9],
  s12_7[8],
  s12_7[7],
  s12_7[6],
  s12_7[5],
  s12_7[4],
  s12_7[3],
  s12_7[2],
  s12_7[1],
  s12_7[0]};
assign n7 = n1 ? n5 : n6;
cf_fp_mul_c_11_52_87 s8 (s10_1, s10_2, s8_1, s8_2);
cf_fp_mul_c_11_52_30 s9 (s8_1, s8_2, s9_1, s9_2);
cf_fp_mul_c_11_52_29 s10 (n4, n7, s10_1, s10_2);
cf_fp_mul_c_11_52_22 s11 (s12_1, s12_2, s12_3, s12_4, s12_5, s9_1, s9_2, s11_1);
cf_fp_mul_c_11_52_2 s12 (i1, i2, s12_1, s12_2, s12_3, s12_4, s12_5, s12_6, s12_7);
assign o1 = s11_1;
endmodule

module cf_fp_mul_c_11_52_2 (i1, i2, o1, o2, o3, o4, o5, o6, o7);
input  [63:0] i1;
input  [63:0] i2;
output o1;
output o2;
output o3;
output o4;
output o5;
output [11:0] o6;
output [105:0] o7;
wire   n1;
wire   [10:0] n2;
wire   [51:0] n3;
wire   n4;
wire   [10:0] n5;
wire   [51:0] n6;
wire   n7;
wire   n8;
wire   n9;
wire   n10;
wire   n11;
wire   n12;
wire   n13;
wire   n14;
wire   n15;
wire   n16;
wire   [11:0] n17;
wire   n18;
wire   [11:0] n19;
wire   [11:0] n20;
wire   [11:0] n21;
wire   n22;
wire   [52:0] n23;
wire   n24;
wire   [52:0] n25;
wire   [105:0] n26;
wire   [11:0] n27;
wire   s28_1;
wire   s28_2;
wire   s28_3;
wire   s28_4;
wire   s28_5;
wire   s29_1;
wire   s29_2;
wire   s29_3;
wire   s29_4;
wire   s29_5;
assign n1 = i1[63];
assign n2 = {i1[62],
  i1[61],
  i1[60],
  i1[59],
  i1[58],
  i1[57],
  i1[56],
  i1[55],
  i1[54],
  i1[53],
  i1[52]};
assign n3 = {i1[51],
  i1[50],
  i1[49],
  i1[48],
  i1[47],
  i1[46],
  i1[45],
  i1[44],
  i1[43],
  i1[42],
  i1[41],
  i1[40],
  i1[39],
  i1[38],
  i1[37],
  i1[36],
  i1[35],
  i1[34],
  i1[33],
  i1[32],
  i1[31],
  i1[30],
  i1[29],
  i1[28],
  i1[27],
  i1[26],
  i1[25],
  i1[24],
  i1[23],
  i1[22],
  i1[21],
  i1[20],
  i1[19],
  i1[18],
  i1[17],
  i1[16],
  i1[15],
  i1[14],
  i1[13],
  i1[12],
  i1[11],
  i1[10],
  i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n4 = i2[63];
assign n5 = {i2[62],
  i2[61],
  i2[60],
  i2[59],
  i2[58],
  i2[57],
  i2[56],
  i2[55],
  i2[54],
  i2[53],
  i2[52]};
assign n6 = {i2[51],
  i2[50],
  i2[49],
  i2[48],
  i2[47],
  i2[46],
  i2[45],
  i2[44],
  i2[43],
  i2[42],
  i2[41],
  i2[40],
  i2[39],
  i2[38],
  i2[37],
  i2[36],
  i2[35],
  i2[34],
  i2[33],
  i2[32],
  i2[31],
  i2[30],
  i2[29],
  i2[28],
  i2[27],
  i2[26],
  i2[25],
  i2[24],
  i2[23],
  i2[22],
  i2[21],
  i2[20],
  i2[19],
  i2[18],
  i2[17],
  i2[16],
  i2[15],
  i2[14],
  i2[13],
  i2[12],
  i2[11],
  i2[10],
  i2[9],
  i2[8],
  i2[7],
  i2[6],
  i2[5],
  i2[4],
  i2[3],
  i2[2],
  i2[1],
  i2[0]};
assign n7 = s29_2 | s29_1;
assign n8 = s28_2 | s28_1;
assign n9 = n7 | n8;
assign n10 = s29_3 & s28_4;
assign n11 = s29_4 & s28_3;
assign n12 = n10 | n11;
assign n13 = s29_3 | s28_3;
assign n14 = s29_4 | s28_4;
assign n15 = n1 ^ n4;
assign n16 = 1'b0;
assign n17 = {n16, n2};
assign n18 = 1'b0;
assign n19 = {n18, n5};
assign n20 = n17 + n19;
assign n21 = n20 - n27;
assign n22 = ~s29_5;
assign n23 = {n22, n3};
assign n24 = ~s28_5;
assign n25 = {n24, n6};
assign n26 = {{53{1'b0}}, n23} * {{53{1'b0}}, n25};
assign n27 = 12'b001111111111;
cf_fp_mul_c_11_52_3 s28 (i2, s28_1, s28_2, s28_3, s28_4, s28_5);
cf_fp_mul_c_11_52_3 s29 (i1, s29_1, s29_2, s29_3, s29_4, s29_5);
assign o7 = n26;
assign o6 = n21;
assign o5 = n15;
assign o4 = n14;
assign o3 = n13;
assign o2 = n12;
assign o1 = n9;
endmodule

module cf_fp_mul_c_11_52_3 (i1, o1, o2, o3, o4, o5);
input  [63:0] i1;
output o1;
output o2;
output o3;
output o4;
output o5;
wire   [10:0] n1;
wire   [51:0] n2;
wire   n3;
wire   [9:0] n4;
wire   n5;
wire   [8:0] n6;
wire   n7;
wire   [9:0] n8;
wire   n9;
wire   [8:0] n10;
wire   n11;
wire   n12;
wire   n13;
wire   n14;
wire   n15;
wire   n16;
wire   n17;
wire   n18;
wire   n19;
wire   n20;
wire   n21;
wire   n22;
wire   s23_1;
wire   s23_2;
wire   s23_3;
wire   s23_4;
wire   s23_5;
wire   s23_6;
wire   s23_7;
wire   s23_8;
wire   s23_9;
wire   s24_1;
wire   s25_1;
wire   s25_2;
wire   s25_3;
wire   s25_4;
wire   s25_5;
wire   s25_6;
wire   s25_7;
wire   s25_8;
wire   s25_9;
wire   s26_1;
wire   s27_1;
assign n1 = {i1[62],
  i1[61],
  i1[60],
  i1[59],
  i1[58],
  i1[57],
  i1[56],
  i1[55],
  i1[54],
  i1[53],
  i1[52]};
assign n2 = {i1[51],
  i1[50],
  i1[49],
  i1[48],
  i1[47],
  i1[46],
  i1[45],
  i1[44],
  i1[43],
  i1[42],
  i1[41],
  i1[40],
  i1[39],
  i1[38],
  i1[37],
  i1[36],
  i1[35],
  i1[34],
  i1[33],
  i1[32],
  i1[31],
  i1[30],
  i1[29],
  i1[28],
  i1[27],
  i1[26],
  i1[25],
  i1[24],
  i1[23],
  i1[22],
  i1[21],
  i1[20],
  i1[19],
  i1[18],
  i1[17],
  i1[16],
  i1[15],
  i1[14],
  i1[13],
  i1[12],
  i1[11],
  i1[10],
  i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n1[10];
assign n4 = {n1[9],
  n1[8],
  n1[7],
  n1[6],
  n1[5],
  n1[4],
  n1[3],
  n1[2],
  n1[1],
  n1[0]};
assign n5 = n4[9];
assign n6 = {n4[8],
  n4[7],
  n4[6],
  n4[5],
  n4[4],
  n4[3],
  n4[2],
  n4[1],
  n4[0]};
assign n7 = n1[10];
assign n8 = {n1[9],
  n1[8],
  n1[7],
  n1[6],
  n1[5],
  n1[4],
  n1[3],
  n1[2],
  n1[1],
  n1[0]};
assign n9 = n8[9];
assign n10 = {n8[8],
  n8[7],
  n8[6],
  n8[5],
  n8[4],
  n8[3],
  n8[2],
  n8[1],
  n8[0]};
assign n11 = ~s26_1;
assign n12 = n2[51];
assign n13 = s24_1 & n12;
assign n14 = n2[51];
assign n15 = ~n14;
assign n16 = s24_1 & n15;
assign n17 = ~s27_1;
assign n18 = n16 & n17;
assign n19 = s24_1 & s27_1;
assign n20 = n11 & s27_1;
assign n21 = ~s27_1;
assign n22 = n11 & n21;
cf_fp_mul_c_11_52_90 s23 (n6, s23_1, s23_2, s23_3, s23_4, s23_5, s23_6, s23_7, s23_8, s23_9);
cf_fp_mul_c_11_52_21 s24 (n3, n5, s23_1, s23_2, s23_3, s23_4, s23_5, s23_6, s23_7, s23_8, s23_9, s24_1);
cf_fp_mul_c_11_52_90 s25 (n10, s25_1, s25_2, s25_3, s25_4, s25_5, s25_6, s25_7, s25_8, s25_9);
cf_fp_mul_c_11_52_20 s26 (n7, n9, s25_1, s25_2, s25_3, s25_4, s25_5, s25_6, s25_7, s25_8, s25_9, s26_1);
cf_fp_mul_c_11_52_4 s27 (n2, s27_1);
assign o5 = n22;
assign o4 = n20;
assign o3 = n19;
assign o2 = n18;
assign o1 = n13;
endmodule

module cf_fp_mul_c_11_52_4 (i1, o1);
input  [51:0] i1;
output o1;
wire   n1;
wire   [50:0] n2;
wire   n3;
wire   [49:0] n4;
wire   n5;
wire   [48:0] n6;
wire   n7;
wire   s8_1;
wire   s8_2;
wire   s8_3;
wire   s8_4;
wire   s8_5;
wire   s8_6;
wire   s8_7;
wire   s8_8;
wire   s8_9;
wire   s8_10;
wire   s8_11;
wire   s8_12;
wire   s8_13;
wire   s8_14;
wire   s8_15;
wire   s8_16;
wire   s8_17;
wire   s8_18;
wire   s8_19;
wire   s8_20;
wire   s8_21;
wire   s8_22;
wire   s8_23;
wire   s8_24;
wire   s8_25;
wire   s8_26;
wire   s8_27;
wire   s8_28;
wire   s8_29;
wire   s8_30;
wire   s8_31;
wire   s8_32;
wire   s8_33;
wire   s8_34;
wire   s8_35;
wire   s8_36;
wire   s8_37;
wire   s8_38;
wire   s8_39;
wire   s8_40;
wire   s8_41;
wire   s8_42;
wire   s8_43;
wire   s8_44;
wire   s8_45;
wire   s8_46;
wire   s8_47;
wire   s8_48;
wire   s8_49;
wire   s9_1;
assign n1 = i1[51];
assign n2 = {i1[50],
  i1[49],
  i1[48],
  i1[47],
  i1[46],
  i1[45],
  i1[44],
  i1[43],
  i1[42],
  i1[41],
  i1[40],
  i1[39],
  i1[38],
  i1[37],
  i1[36],
  i1[35],
  i1[34],
  i1[33],
  i1[32],
  i1[31],
  i1[30],
  i1[29],
  i1[28],
  i1[27],
  i1[26],
  i1[25],
  i1[24],
  i1[23],
  i1[22],
  i1[21],
  i1[20],
  i1[19],
  i1[18],
  i1[17],
  i1[16],
  i1[15],
  i1[14],
  i1[13],
  i1[12],
  i1[11],
  i1[10],
  i1[9],
  i1[8],
  i1[7],
  i1[6],
  i1[5],
  i1[4],
  i1[3],
  i1[2],
  i1[1],
  i1[0]};
assign n3 = n2[50];
assign n4 = {n2[49],
  n2[48],
  n2[47],
  n2[46],
  n2[45],
  n2[44],
  n2[43],
  n2[42],
  n2[41],
  n2[40],
  n2[39],
  n2[38],
  n2[37],
  n2[36],
  n2[35],
  n2[34],
  n2[33],
  n2[32],
  n2[31],
  n2[30],
  n2[29],
  n2[28],
  n2[27],
  n2[26],
  n2[25],
  n2[24],
  n2[23],
  n2[22],
  n2[21],
  n2[20],
  n2[19],
  n2[18],
  n2[17],
  n2[16],
  n2[15],
  n2[14],
  n2[13],
  n2[12],
  n2[11],
  n2[10],
  n2[9],
  n2[8],
  n2[7],
  n2[6],
  n2[5],
  n2[4],
  n2[3],
  n2[2],
  n2[1],
  n2[0]};
assign n5 = n4[49];
assign n6 = {n4[48],
  n4[47],
  n4[46],
  n4[45],
  n4[44],
  n4[43],
  n4[42],
  n4[41],
  n4[40],
  n4[39],