uart.map.rpt

一个串口的完整FPGA工程

; UDR            ; 00000    ; Unsigned Binary           ;
; UCSRA          ; 00001    ; Unsigned Binary           ;
; UCSRB          ; 00010    ; Unsigned Binary           ;
; UCSRC          ; 00011    ; Unsigned Binary           ;
; UBRRH          ; 00100    ; Unsigned Binary           ;
; UBRRL          ; 00101    ; Unsigned Binary           ;
; UVER           ; 00110    ; Unsigned Binary           ;
; UDEBUG         ; 00111    ; Unsigned Binary           ;
; RXC            ; 7        ; Signed Integer            ;
; TXC            ; 6        ; Signed Integer            ;
; UDRE           ; 5        ; Signed Integer            ;
; FE             ; 4        ; Signed Integer            ;
; DOR            ; 3        ; Signed Integer            ;
; UPE            ; 2        ; Signed Integer            ;
; U2X            ; 1        ; Signed Integer            ;
; MPCM           ; 0        ; Signed Integer            ;
; RXCIE          ; 7        ; Signed Integer            ;
; TXCIE          ; 6        ; Signed Integer            ;
; UDRIE          ; 5        ; Signed Integer            ;
; RXEN           ; 4        ; Signed Integer            ;
; TXEN           ; 3        ; Signed Integer            ;
; UCSZ2          ; 2        ; Signed Integer            ;
; RXB8           ; 1        ; Signed Integer            ;
; TXB8           ; 0        ; Signed Integer            ;
; UMSEL          ; 6        ; Signed Integer            ;
; UPM1           ; 5        ; Signed Integer            ;
; UPM0           ; 4        ; Signed Integer            ;
; USBS           ; 3        ; Signed Integer            ;
; UCSZ1          ; 2        ; Signed Integer            ;
; UCSZ0          ; 1        ; Signed Integer            ;
; UCPOL          ; 0        ; Signed Integer            ;
+----------------+----------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart:U_2|rxd:U_receiver ;
+----------------+---------+-------------------------------------------+
; Parameter Name ; Value   ; Type                                      ;
+----------------+---------+-------------------------------------------+
; RX_IDLE        ; 0000001 ; Unsigned Binary                           ;
; RX_SYNC        ; 0000010 ; Unsigned Binary                           ;
; RX_DATA        ; 0000100 ; Unsigned Binary                           ;
; RX_PARITY      ; 0001000 ; Unsigned Binary                           ;
; RX_STOP        ; 0010000 ; Unsigned Binary                           ;
; RX_ENDING      ; 0100000 ; Unsigned Binary                           ;
; RX_DONE        ; 1000000 ; Unsigned Binary                           ;
+----------------+---------+-------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart:U_2|txd:U_transmitter ;
+----------------+----------+---------------------------------------------+
; Parameter Name ; Value    ; Type                                        ;
+----------------+----------+---------------------------------------------+
; TX_IDLE        ; 00000001 ; Unsigned Binary                             ;
; TX_READY       ; 00000010 ; Unsigned Binary                             ;
; TX_START       ; 00000100 ; Unsigned Binary                             ;
; TX_DATA        ; 00001000 ; Unsigned Binary                             ;
; TX_PARITY      ; 00010000 ; Unsigned Binary                             ;
; TX_STOP1       ; 00100000 ; Unsigned Binary                             ;
; TX_STOP2       ; 01000000 ; Unsigned Binary                             ;
; TX_DONE        ; 10000000 ; Unsigned Binary                             ;
+----------------+----------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu May 07 23:21:39 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uart -c uart
Info: Found 1 design units, including 1 entities, in source file src/divider.v
    Info: Found entity 1: divider
Info: Found 1 design units, including 1 entities, in source file src/ebi.v
    Info: Found entity 1: ebi
Info: Found 1 design units, including 1 entities, in source file src/rxd.v
    Info: Found entity 1: rxd
Info: Found 1 design units, including 1 entities, in source file src/top.v
    Info: Found entity 1: top
Info: Found 1 design units, including 1 entities, in source file src/txd.v
    Info: Found entity 1: txd
Info: Found 1 design units, including 1 entities, in source file src/uart.v
    Info: Found entity 1: uart
Info: Elaborating entity "top" for the top level hierarchy
Info: Elaborating entity "ebi" for hierarchy "ebi:U_1"
Warning (10240): Verilog HDL Always Construct warning at ebi.v(47): inferring latch(es) for variable "rAddrL", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "rAddrL[0]" at ebi.v(47)
Info (10041): Inferred latch for "rAddrL[1]" at ebi.v(47)
Info (10041): Inferred latch for "rAddrL[2]" at ebi.v(47)
Info (10041): Inferred latch for "rAddrL[3]" at ebi.v(47)
Info (10041): Inferred latch for "rAddrL[4]" at ebi.v(47)
Info (10041): Inferred latch for "rAddrL[5]" at ebi.v(47)
Info (10041): Inferred latch for "rAddrL[6]" at ebi.v(47)
Info (10041): Inferred latch for "rAddrL[7]" at ebi.v(47)
Info: Elaborating entity "uart" for hierarchy "uart:U_2"
Info: Elaborating entity "divider" for hierarchy "uart:U_2|divider:U_divider"
Info: Elaborating entity "rxd" for hierarchy "uart:U_2|rxd:U_receiver"
Info: Elaborating entity "txd" for hierarchy "uart:U_2|txd:U_transmitter"
Info (10264): Verilog HDL Case Statement information at txd.v(265): all case item expressions in this case statement are onehot
Info: State machine "|top|uart:U_2|txd:U_transmitter|rStatTxCur" contains 8 states
Info: State machine "|top|uart:U_2|rxd:U_receiver|rStatRxCur" contains 7 states
Info: Selected Auto state machine encoding method for state machine "|top|uart:U_2|txd:U_transmitter|rStatTxCur"
Info: State machine "|top|uart:U_2|txd:U_transmitter|rStatTxCur" will be implemented as a safe state machine.
Info: Encoding result for state machine "|top|uart:U_2|txd:U_transmitter|rStatTxCur"
    Info: Completed encoding using 8 state bits
        Info: Encoded state bit "uart:U_2|txd:U_transmitter|rStatTxCur.TX_DONE"
        Info: Encoded state bit "uart:U_2|txd:U_transmitter|rStatTxCur.TX_STOP2"
        Info: Encoded state bit "uart:U_2|txd:U_transmitter|rStatTxCur.TX_STOP1"
        Info: Encoded state bit "uart:U_2|txd:U_transmitter|rStatTxCur.TX_PARITY"
        Info: Encoded state bit "uart:U_2|txd:U_transmitter|rStatTxCur.TX_DATA"
        Info: Encoded state bit "uart:U_2|txd:U_transmitter|rStatTxCur.TX_START"
        Info: Encoded state bit "uart:U_2|txd:U_transmitter|rStatTxCur.TX_READY"
        Info: Encoded state bit "uart:U_2|txd:U_transmitter|rStatTxCur.TX_IDLE"
    Info: State "|top|uart:U_2|txd:U_transmitter|rStatTxCur.TX_IDLE" uses code string "00000000"
    Info: State "|top|uart:U_2|txd:U_transmitter|rStatTxCur.TX_READY" uses code string "00000011"
    Info: State "|top|uart:U_2|txd:U_transmitter|rStatTxCur.TX_START" uses code string "00000101"
    Info: State "|top|uart:U_2|txd:U_transmitter|rStatTxCur.TX_DATA" uses code string "00001001"
    Info: State "|top|uart:U_2|txd:U_transmitter|rStatTxCur.TX_PARITY" uses code string "00010001"
    Info: State "|top|uart:U_2|txd:U_transmitter|rStatTxCur.TX_STOP1" uses code string "00100001"
    Info: State "|top|uart:U_2|txd:U_transmitter|rStatTxCur.TX_STOP2" uses code string "01000001"
    Info: State "|top|uart:U_2|txd:U_transmitter|rStatTxCur.TX_DONE" uses code string "10000001"
Info: Selected Auto state machine encoding method for state machine "|top|uart:U_2|rxd:U_receiver|rStatRxCur"
Info: State machine "|top|uart:U_2|rxd:U_receiver|rStatRxCur" will be implemented as a safe state machine.
Info: Encoding result for state machine "|top|uart:U_2|rxd:U_receiver|rStatRxCur"
    Info: Completed encoding using 7 state bits
        Info: Encoded state bit "uart:U_2|rxd:U_receiver|rStatRxCur.RX_DONE"
        Info: Encoded state bit "uart:U_2|rxd:U_receiver|rStatRxCur.RX_ENDING"
        Info: Encoded state bit "uart:U_2|rxd:U_receiver|rStatRxCur.RX_STOP"
        Info: Encoded state bit "uart:U_2|rxd:U_receiver|rStatRxCur.RX_PARITY"
        Info: Encoded state bit "uart:U_2|rxd:U_receiver|rStatRxCur.RX_DATA"
        Info: Encoded state bit "uart:U_2|rxd:U_receiver|rStatRxCur.RX_SYNC"
        Info: Encoded state bit "uart:U_2|rxd:U_receiver|rStatRxCur.RX_IDLE"
    Info: State "|top|uart:U_2|rxd:U_receiver|rStatRxCur.RX_IDLE" uses code string "0000000"
    Info: State "|top|uart:U_2|rxd:U_receiver|rStatRxCur.RX_SYNC" uses code string "0000011"
    Info: State "|top|uart:U_2|rxd:U_receiver|rStatRxCur.RX_DATA" uses code string "0000101"
    Info: State "|top|uart:U_2|rxd:U_receiver|rStatRxCur.RX_PARITY" uses code string "0001001"
    Info: State "|top|uart:U_2|rxd:U_receiver|rStatRxCur.RX_STOP" uses code string "0010001"
    Info: State "|top|uart:U_2|rxd:U_receiver|rStatRxCur.RX_ENDING" uses code string "0100001"
    Info: State "|top|uart:U_2|rxd:U_receiver|rStatRxCur.RX_DONE" uses code string "1000001"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "uart_clk" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 266 device resources after synthesis - the final resource count might be different
    Info: Implemented 14 input pins
    Info: Implemented 3 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 241 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 142 megabytes of memory during processing
    Info: Processing ended: Thu May 07 23:21:46 2009
    Info: Elapsed time: 00:00:07