_primary.vhd

来自「一个串口的完整FPGA工程」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity ebi is
    port(
        clk             : in     vl_logic;
        ebi_ad          : inout  vl_logic_vector(7 downto 0);
        ebi_addr_h      : in     vl_logic_vector(7 downto 0);
        ebi_wr_n        : in     vl_logic;
        ebi_rd_n        : in     vl_logic;
        ebi_ale         : in     vl_logic;
        we              : out    vl_logic;
        data_in         : in     vl_logic_vector(7 downto 0);
        data_out        : out    vl_logic_vector(7 downto 0);
        addr_out        : out    vl_logic_vector(15 downto 0)
    );
end ebi;